104 lines
3.8 KiB
C
104 lines
3.8 KiB
C
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/*
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* i2cCore.h
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*
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* Prototypes, etc. for the Motorola MPC8220
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* embedded cpu chips
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*
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* 2004 (c) Freescale, Inc.
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* Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __INCi2ccoreh
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#define __INCi2ccoreh
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#ifndef __ASSEMBLY__
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/* device types */
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#define I2C_DEVICE_TYPE_EEPROM 0
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#define I2C_EEPROM_ADRS 0xa0
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#define I2C_CTRL_ADRS I2C_EEPROM_ADRS
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#define EEPROM_ADDR0 0xA2 /* on Dimm SPD eeprom */
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#define EEPROM_ADDR1 0xA4 /* on Board SPD eeprom */
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#define EEPROM_ADDR2 0xD2 /* non-standard eeprom - clock generator */
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/* Control Register */
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#define I2C_CTL_EN 0x80 /* I2C Enable */
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#define I2C_CTL_IEN 0x40 /* I2C Interrupt Enable */
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#define I2C_CTL_STA 0x20 /* Master/Slave Mode select */
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#define I2C_CTL_TX 0x10 /* Transmit/Receive Mode Select */
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#define I2C_CTL_TXAK 0x08 /* Transmit Acknowledge Enable */
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#define I2C_CTL_RSTA 0x04 /* Repeat Start */
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/* Status Register */
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#define I2C_STA_CF 0x80 /* Data Transfer */
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#define I2C_STA_AAS 0x40 /* Adressed As Slave */
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#define I2C_STA_BB 0x20 /* Bus Busy */
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#define I2C_STA_AL 0x10 /* Arbitration Lost */
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#define I2C_STA_SRW 0x04 /* Slave Read/Write */
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#define I2C_STA_IF 0x02 /* I2C Interrupt */
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#define I2C_STA_RXAK 0x01 /* Receive Acknowledge */
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/* Interrupt Contol Register */
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#define I2C_INT_BNBE2 0x80 /* Bus Not Busy Enable 2 */
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#define I2C_INT_TE2 0x40 /* Transmit Enable 2 */
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#define I2C_INT_RE2 0x20 /* Receive Enable 2 */
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#define I2C_INT_IE2 0x10 /* Interrupt Enable 2 */
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#define I2C_INT_BNBE1 0x08 /* Bus Not Busy Enable 1 */
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#define I2C_INT_TE1 0x04 /* Transmit Enable 1 */
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#define I2C_INT_RE1 0x02 /* Receive Enable 1 */
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#define I2C_INT_IE1 0x01 /* Interrupt Enable 1 */
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#define I2C_POLL_COUNT 0x100000
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#define I2C_ENABLE 0x00000001
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#define I2C_DISABLE 0x00000002
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#define I2C_START 0x00000004
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#define I2C_REPSTART 0x00000008
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#define I2C_STOP 0x00000010
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#define I2C_BITRATE 0x00000020
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#define I2C_SLAVEADR 0x00000040
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#define I2C_STARTADR 0x00000080
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#undef TWOBYTES
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typedef struct i2c_settings {
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/* Device settings */
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int bit_rate; /* Device bit rate */
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u8 i2c_adr; /* I2C address */
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u8 slv_adr; /* Slave address */
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#ifdef TWOBYTES
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u16 str_adr; /* Start address */
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#else
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u8 str_adr; /* Start address */
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#endif
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int xfer_size; /* Transfer Size */
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int bI2c_en; /* Enable or Disable */
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int cmdFlag; /* I2c Command Flags */
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} i2cset_t;
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/*
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int check_status(PSI2C pi2c, u8 sta_bit, u8 truefalse);
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int i2c_enable(PSI2C pi2c, PI2CSET pi2cSet);
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int i2c_disable(PSI2C pi2c);
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int i2c_start(PSI2C pi2c, PI2CSET pi2cSet);
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int i2c_stop(PSI2C pi2c);
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int i2c_clear(PSI2C pi2c);
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int i2c_readblock (PSI2C pi2c, PI2CSET pi2cSet, u8 *Data);
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int i2c_writeblock (PSI2C pi2c, PI2CSET pi2cSet, u8 *Data);
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int i2c_readbyte(PSI2C pi2c, u8 *readb, int *index);
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int i2c_writebyte(PSI2C pi2c, u8 *writeb);
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int SetI2cFDR( PSI2C pi2cRegs, int bitrate );
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*/
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#endif /* __ASSEMBLY__ */
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#endif /* __INCi2ccoreh */
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