100 lines
4.0 KiB
C
100 lines
4.0 KiB
C
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/*
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* mcf5272.h -- Definitions for Motorola Coldfire 5272
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*
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* Based on mcf5272sim.h of uCLinux distribution:
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* (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
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* (C) Copyright 2000, Lineo Inc. (www.lineo.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef mcf5272_h
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#define mcf5272_h
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/****************************************************************************/
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/*
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* Size of internal RAM
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*/
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#define INT_RAM_SIZE 4096
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/*
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* Define the 5272 SIM register set addresses.
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*/
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#define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */
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#define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/
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#define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */
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#define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */
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#define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */
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#define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */
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#define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */
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#define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */
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#define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */
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#define MCFSIM_ISR 0x30 /* Interrupt Source reg (r/w) */
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#define MCFSIM_PITR 0x34 /* Interrupt Transition (r/w) */
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#define MCFSIM_PIWR 0x38 /* Interrupt Wakeup reg (r/w) */
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#define MCFSIM_PIVR 0x3f /* Interrupt Vector reg (r/w( */
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#define MCFSIM_WRRR 0x280 /* Watchdog reference (r/w) */
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#define MCFSIM_WIRR 0x284 /* Watchdog interrupt (r/w) */
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#define MCFSIM_WCR 0x288 /* Watchdog counter (r/w) */
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#define MCFSIM_WER 0x28c /* Watchdog event (r/w) */
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#define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */
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#define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */
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#define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */
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#define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */
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#define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */
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#define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */
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#define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */
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#define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */
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#define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */
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#define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */
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#define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */
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#define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */
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#define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */
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#define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */
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#define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */
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#define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */
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#define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */
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#define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */
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#define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */
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#define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */
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#define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */
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#define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */
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#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */
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#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */
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#define MCFSIM_PACNT 0x80 /* Port A Control (r/w) */
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#define MCFSIM_PADDR 0x84 /* Port A Direction (r/w) */
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#define MCFSIM_PADAT 0x86 /* Port A Data (r/w) */
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#define MCFSIM_PBCNT 0x88 /* Port B Control (r/w) */
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#define MCFSIM_PBDDR 0x8c /* Port B Direction (r/w) */
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#define MCFSIM_PBDAT 0x8e /* Port B Data (r/w) */
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#define MCFSIM_PCDDR 0x94 /* Port C Direction (r/w) */
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#define MCFSIM_PCDAT 0x96 /* Port C Data (r/w) */
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#define MCFSIM_PDCNT 0x98 /* Port D Control (r/w) */
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#endif /* mcf5272_h */
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