204 lines
6.8 KiB
C
204 lines
6.8 KiB
C
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/*
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* Copyright (C) 2004 Arabella Software Ltd.
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* Yuli Barcohen <yuli@arabellasw.com>
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*
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* Support for Analogue&Micro Adder boards family.
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* Tested on AdderII and Adder87x.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#if !defined(CONFIG_MPC875) && !defined(CONFIG_MPC852T)
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#define CONFIG_MPC875
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#endif
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#define CONFIG_ADDER /* Analogue&Micro Adder board */
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#define CONFIG_BAUDRATE 38400
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#define CONFIG_FEC_ENET /* Ethernet is on FEC */
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#ifdef CONFIG_FEC_ENET
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#define CFG_DISCOVER_PHY
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#define FEC_ENET
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#endif /* CONFIG_FEC_ENET */
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#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
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#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
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#define CFG_8xx_CPUCLK_MIN 40000000
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#ifdef CONFIG_MPC852T
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#define CFG_8xx_CPUCLK_MAX 50000000
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#else
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#define CFG_8xx_CPUCLK_MAX 120000000
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#endif /* CONFIG_MPC852T */
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
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| CFG_CMD_DHCP \
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| CFG_CMD_IMMAP \
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| CFG_CMD_MII \
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| CFG_CMD_PING \
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)
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/* This must be included AFTER the definition of CONFIG_COMMANDS */
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#include <cmd_confdefs.h>
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#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */
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#define CONFIG_BOOTCOMMAND "bootm fe040000" /* Autoboot command */
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#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw"
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#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
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#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */
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/*-----------------------------------------------------------------------
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* Miscellaneous configurable options
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*/
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#define CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#define CFG_LONGHELP /* #undef to save memory */
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* Max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_LOAD_ADDR 0x100000 /* Default load address */
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#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*-----------------------------------------------------------------------
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* RAM configuration (note that CFG_SDRAM_BASE must be zero)
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */
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#define CFG_OR1_PRELIM (0xFF800000 | OR_CSNT_SAM | OR_ACS_DIV2)
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#define CFG_BR1_PRELIM (CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V)
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#define CFG_MAMR 0x00802114
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/*
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* 2048 SDRAM rows
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* 1000 factor s -> ms
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* 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
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* 4 Number of refresh cycles per period
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* 64 Refresh cycle in ms per number of rows
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*/
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#define CFG_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64))
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#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
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#define CFG_MEMTEST_END 0x00700000 /* 1 ... 7 MB in SDRAM */
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#define CFG_RESET_ADDRESS 0x09900000
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/*-----------------------------------------------------------------------
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 KB for Monitor */
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#ifdef CONFIG_BZIP2
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#define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
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#else
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
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#endif /* CONFIG_BZIP2 */
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/*-----------------------------------------------------------------------
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* Flash organisation
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*/
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#define CFG_FLASH_BASE 0xFE000000
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#define CFG_FLASH_CFI /* The flash is CFI compatible */
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#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
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#define CFG_MAX_FLASH_SECT 128 /* Max num of sects on one chip */
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/* Environment is in flash */
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#define CFG_ENV_IS_IN_FLASH
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#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
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#define CFG_OR0_PRELIM 0xFF000774
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#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V)
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#define CFG_DIRECT_FLASH_TFTP
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/*-----------------------------------------------------------------------
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* Internal Memory Map Register
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*/
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#define CFG_IMMR 0xFF000000
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Configuration registers
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*/
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#ifdef CONFIG_WATCHDOG
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
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SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \
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SYPCR_SWP)
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#else
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
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SYPCR_SWF | SYPCR_SWP)
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#endif /* CONFIG_WATCHDOG */
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#define CFG_SIUMCR (SIUMCR_MLRC01 | SIUMCR_DBGC11)
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/* TBSCR - Time Base Status and Control Register */
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#define CFG_TBSCR (TBSCR_TBF | TBSCR_TBE)
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/* PISCR - Periodic Interrupt Status and Control */
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#define CFG_PISCR (PISCR_PS | PISCR_PITF)
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/* PLPRCR - PLL, Low-Power, and Reset Control Register */
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/* #define CFG_PLPRCR PLPRCR_TEXPS */
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/* SCCR - System Clock and reset Control Register */
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#define SCCR_MASK SCCR_EBDF11
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#define CFG_SCCR SCCR_RTSEL
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#define CFG_DER 0
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx chips */
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/*-----------------------------------------------------------------------
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#endif /* __CONFIG_H */
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