479 lines
17 KiB
C
479 lines
17 KiB
C
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/*
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* (C) Copyright 2001-2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* configuration options, board specific, for Siemens Card Controller Module
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#undef CCM_80MHz /* define for 80 MHz CPU only */
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC860 1 /* This is a MPC860 CPU ... */
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#define CONFIG_CCM 1 /* on a Card Controller Module */
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#undef CONFIG_8xx_CONS_SMC2
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#undef CONFIG_8xx_CONS_NONE
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/* ENVIRONMENT */
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#define CONFIG_BAUDRATE 19200 /* console baudrate in bps */
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#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
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#define CONFIG_IPADDR 192.168.0.42
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_GATEWAYIP 0.0.0.0
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#define CONFIG_SERVERIP 192.168.0.254
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#define CONFIG_HOSTNAME CCM
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#define CONFIG_LOADADDR 40180000
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#undef CONFIG_BOOTARGS
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#define CONFIG_BOOTCOMMAND "setenv bootargs " \
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"mem=${mem} " \
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"root=/dev/ram rw ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
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"wt_8xx=timeout:3600; " \
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"bootm"
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
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#define CONFIG_WATCHDOG 1 /* watchdog enabled */
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#undef CONFIG_STATUS_LED /* Status LED disabled */
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#define CONFIG_PRAM 512 /* reserve 512kB "protected RAM"*/
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#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
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#define CONFIG_SPI /* enable SPI driver */
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#define CONFIG_SPI_X /* 16 bit EEPROM addressing */
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/* ----------------------------------------------------------------
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* Offset to initial SPI buffers in DPRAM (used if the environment
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* is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to
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* use at an early stage. It is used between the two initialization
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* calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it
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* far enough from the start of the data area (as well as from the
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* stack pointer).
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* ---------------------------------------------------------------- */
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#define CFG_SPI_INIT_OFFSET 0xB00
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#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32-byte page size */
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#define CONFIG_MAC_PARTITION /* nod used yet */
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#define CONFIG_DOS_PARTITION
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#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
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CFG_CMD_BSP | \
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CFG_CMD_DHCP | \
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CFG_CMD_DATE | \
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CFG_CMD_EEPROM | \
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CFG_CMD_NFS | \
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CFG_CMD_SNTP )
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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/*----------------------------------------------------------------------*/
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
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#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
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#define CFG_LOAD_ADDR 0x00100000 /* default load address */
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/* Ethernet hardware configuration done using port pins */
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#define CFG_PA_ETH_RESET 0x0200 /* PA 6 */
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#define CFG_PA_ETH_MDDIS 0x4000 /* PA 1 */
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#define CFG_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */
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#define CFG_PB_ETH_CFG1 0x00000400 /* PB 21 */
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#define CFG_PB_ETH_CFG2 0x00000200 /* PB 22 */
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#define CFG_PB_ETH_CFG3 0x00000100 /* PB 23 */
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/* Ethernet settings:
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* MDIO not disabled, autonegotiation, 10/100Mbps, half/full duplex
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*/
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#define CFG_ETH_MDDIS_VALUE 0
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#define CFG_ETH_CFG1_VALUE 1
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#define CFG_ETH_CFG2_VALUE 1
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#define CFG_ETH_CFG3_VALUE 1
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/* PUMA configuration */
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#define CFG_PC_PUMA_PROG 0x0200 /* PC 6 */
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#define CFG_PC_PUMA_DONE 0x0008 /* PC 12 */
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#define CFG_PC_PUMA_INIT 0x0004 /* PC 13 */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CFG_IMMR 0xF0000000
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Address accessed to reset the board - must not be mapped/assigned
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*/
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#define CFG_RESET_ADDRESS 0xFEFFFFFF
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0x40000000
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#if defined(DEBUG)
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#else
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#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
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#endif
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#if 1
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/* Start port with environment in flash; switch to SPI EEPROM later */
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
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#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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#else
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/* Final version: environment in EEPROM */
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#define CFG_ENV_IS_IN_EEPROM 1
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#define CFG_ENV_OFFSET 2048
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#define CFG_ENV_SIZE 2048
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#endif
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/*-----------------------------------------------------------------------
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* Hardware Information Block
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*/
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#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
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#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
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#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#if defined(CONFIG_WATCHDOG)
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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#else
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWP)
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#endif
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6
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*-----------------------------------------------------------------------
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* we must activate GPL5 in the SIUMCR for CAN
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*/
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#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
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/*-----------------------------------------------------------------------
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* RTCSC - Real-Time Clock Status and Control Register 11-27
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*-----------------------------------------------------------------------
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*/
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#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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*/
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#define CFG_PISCR (PISCR_PS | PISCR_PITF)
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
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*-----------------------------------------------------------------------
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* Reset PLL lock status sticky bit, timer expired status bit and timer
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* interrupt status bit
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*
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* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
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*/
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#ifdef CCM_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
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#define CFG_PLPRCR \
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( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
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#else /* up to 50 MHz we use a 1:1 clock */
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#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
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#endif /* CCM_80MHz */
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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*-----------------------------------------------------------------------
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* Set clock output, timebase and RTC source and divider,
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* power management and some other internal clocks
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*/
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#define SCCR_MASK SCCR_EBDF11
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#ifdef CCM_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
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#define CFG_SCCR (/* SCCR_TBS | */ \
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SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
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SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
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SCCR_DFALCD00)
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#else /* up to 50 MHz we use a 1:1 clock */
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#define CFG_SCCR (SCCR_TBS | \
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SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
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SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
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SCCR_DFALCD00)
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#endif /* CCM_80MHz */
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/*-----------------------------------------------------------------------
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*
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* Interrupt Levels
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*-----------------------------------------------------------------------
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*/
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#define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
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/*-----------------------------------------------------------------------
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*
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*-----------------------------------------------------------------------
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*
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*/
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#define CFG_DER 0
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/*
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* Init Memory Controller:
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*
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* BR0/1 and OR0/1 (FLASH)
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*/
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#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
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#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
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/* used to re-map FLASH both when starting from SRAM or FLASH:
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* restrict access enough to keep SRAM working (if any)
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* but not too much to meddle with FLASH accesses
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*/
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#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
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#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
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/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
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#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
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OR_SCY_5_CLK | OR_EHTR)
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#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
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#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
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#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
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#define CFG_OR1_REMAP CFG_OR0_REMAP
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#define CFG_OR1_PRELIM CFG_OR0_PRELIM
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#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
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/*
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* BR2 and OR2 (SDRAM)
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*
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*/
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#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
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#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
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#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
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/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
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#define CFG_OR_TIMING_SDRAM 0x00000A00
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#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
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#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
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/*
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* BR3 and OR3 (CAN Controller)
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*/
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#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
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#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
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#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
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#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
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BR_PS_8 | BR_MS_UPMB | BR_V )
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/*
|
||
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* BR4/OR4: PUMA Config
|
||
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*
|
||
|
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* Memory controller will be used in 2 modes:
|
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|
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*
|
||
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* - "read" mode:
|
||
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* BR4: 0x10100801 OR4: 0xffff8520
|
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* - "load" mode (chip select on UPM B):
|
||
|
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* BR4: 0x101004c1 OR4: 0xffff8600
|
||
|
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*
|
||
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* Default initialization is in "read" mode
|
||
|
|
*/
|
||
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#define PUMA_CONF_BASE 0x10100000 /* PUMA Config */
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#define PUMA_CONF_OR_AM 0xFFFF8000 /* 32 kB */
|
||
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#define PUMA_CONF_LOAD_TIMING (OR_ACS_DIV2 | OR_SCY_2_CLK)
|
||
|
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#define PUMA_CONF_READ_TIMING (OR_G5LA | OR_BI | OR_SCY_2_CLK)
|
||
|
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|
||
|
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#define PUMA_CONF_BR_LOAD ((PUMA_CONF_BASE & BR_BA_MSK) | \
|
||
|
|
BR_PS_8 | BR_MS_UPMB | BR_V)
|
||
|
|
#define PUMA_CONF_OR_LOAD (PUMA_CONF_OR_AM | PUMA_CONF_LOAD_TIMING)
|
||
|
|
|
||
|
|
#define PUMA_CONF_BR_READ ((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
|
||
|
|
#define PUMA_CONF_OR_READ (PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING)
|
||
|
|
|
||
|
|
#define CFG_BR4_PRELIM PUMA_CONF_BR_READ
|
||
|
|
#define CFG_OR4_PRELIM PUMA_CONF_OR_READ
|
||
|
|
|
||
|
|
/*
|
||
|
|
* BR5/OR5: PUMA: SMA Bus 8 Bit
|
||
|
|
* BR5: 0x10200401 OR5: 0xffe0010a
|
||
|
|
*/
|
||
|
|
#define PUMA_SMA8_BASE 0x10200000 /* PUMA SMA Bus 8 Bit */
|
||
|
|
#define PUMA_SMA8_OR_AM 0xFFE00000 /* 2 MB */
|
||
|
|
#define PUMA_SMA8_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
|
||
|
|
|
||
|
|
#define CFG_BR5_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
|
||
|
|
#define CFG_OR5_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
|
||
|
|
|
||
|
|
/*
|
||
|
|
* BR6/OR6: PUMA: SMA Bus 16 Bit
|
||
|
|
* BR6: 0x10600801 OR6: 0xffe0010a
|
||
|
|
*/
|
||
|
|
#define PUMA_SMA16_BASE 0x10600000 /* PUMA SMA Bus 16 Bit */
|
||
|
|
#define PUMA_SMA16_OR_AM 0xFFE00000 /* 2 MB */
|
||
|
|
#define PUMA_SMA16_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
|
||
|
|
|
||
|
|
#define CFG_BR6_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
|
||
|
|
#define CFG_OR6_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
|
||
|
|
|
||
|
|
/*
|
||
|
|
* BR7/OR7: PUMA: external Flash
|
||
|
|
* BR7: 0x10a00801 OR7: 0xfe00010a
|
||
|
|
*/
|
||
|
|
#define PUMA_FLASH_BASE 0x10A00000 /* PUMA external Flash */
|
||
|
|
#define PUMA_FLASH_OR_AM 0xFE000000 /* 32 MB */
|
||
|
|
#define PUMA_FLASH_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
|
||
|
|
|
||
|
|
#define CFG_BR7_PRELIM ((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
|
||
|
|
#define CFG_OR7_PRELIM (PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA)
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Memory Periodic Timer Prescaler
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* periodic timer for refresh */
|
||
|
|
#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
|
||
|
|
|
||
|
|
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
|
||
|
|
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
|
||
|
|
#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
|
||
|
|
|
||
|
|
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
|
||
|
|
#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
|
||
|
|
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
|
||
|
|
|
||
|
|
/*
|
||
|
|
* MAMR settings for SDRAM
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* 8 column SDRAM */
|
||
|
|
#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||
|
|
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||
|
|
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
||
|
|
/* 9 column SDRAM */
|
||
|
|
#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||
|
|
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||
|
|
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Internal Definitions
|
||
|
|
*
|
||
|
|
* Boot Flags
|
||
|
|
*/
|
||
|
|
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||
|
|
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||
|
|
|
||
|
|
#endif /* __CONFIG_H */
|