457 lines
16 KiB
C
457 lines
16 KiB
C
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/*
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* (C) Copyright 2001-2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <mpc8xx_irq.h>
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC860 1
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#define CONFIG_MPC860T 1
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#define CONFIG_ICU862 1
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#define CONFIG_MPC862 1
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#undef CONFIG_8xx_CONS_SMC2
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#undef CONFIG_8xx_CONS_NONE
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#define CONFIG_BAUDRATE 9600
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#ifdef CONFIG_100MHz
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#define MPC8XX_FACT 24 /* Multiply by 24 */
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#define MPC8XX_XIN 4165000 /* 4.165 MHz in */
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#define CONFIG_8xx_GCLK_FREQ (MPC8XX_FACT * MPC8XX_XIN)
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/* define if cant' use get_gclk_freq */
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#else
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#if 1 /* for 50MHz version of processor */
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#define MPC8XX_FACT 12 /* Multiply by 12 */
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#define MPC8XX_XIN 4000000 /* 4 MHz in */
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#define CONFIG_8xx_GCLK_FREQ 48000000 /* define if cant use get_gclk_freq */
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#else /* for 80MHz version of processor */
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#define MPC8XX_FACT 20 /* Multiply by 20 */
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#define MPC8XX_XIN 4000000 /* 4 MHz in */
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#define CONFIG_8xx_GCLK_FREQ 80000000 /* define if cant use get_gclk_freq */
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#endif
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#endif
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#endif
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#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_BOOTCOMMAND \
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"bootp;" \
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"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
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"bootm"
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_STATUS_LED 1 /* Status LED enabled */
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#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
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#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
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#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
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#define CONFIG_MII 1
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#if 1
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#define CFG_DISCOVER_PHY 1
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#else
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#undef CFG_DISCOVER_PHY
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#endif
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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/* enable I2C and select the hardware/software driver */
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#undef CONFIG_HARD_I2C /* I2C with hardware support */
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#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
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# define CFG_I2C_SPEED 50000
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# define CFG_I2C_SLAVE 0xFE
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# define CFG_I2C_EEPROM_ADDR 0x50
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# define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
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/*
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* Software (bit-bang) I2C driver configuration
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*/
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#define PB_SCL 0x00000020 /* PB 26 */
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#define PB_SDA 0x00000010 /* PB 27 */
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#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
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#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
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#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
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#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
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#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
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else immr->im_cpm.cp_pbdat &= ~PB_SDA
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#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
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else immr->im_cpm.cp_pbdat &= ~PB_SCL
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#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
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#define CFG_EEPROM_X40430 /* Use a Xicor X40430 EEPROM */
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#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 16 bytes page write mode */
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#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
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CFG_CMD_ASKENV | \
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CFG_CMD_DATE | \
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CFG_CMD_DHCP | \
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CFG_CMD_EEPROM | \
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CFG_CMD_I2C | \
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CFG_CMD_IDE | \
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CFG_CMD_NFS | \
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CFG_CMD_SNTP )
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
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#define CFG_LOAD_ADDR 0x00100000
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CFG_IMMR 0xF0000000
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#define CFG_IMMR_SIZE ((uint)(64 * 1024))
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0x40000000
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#define CFG_FLASH_SIZE ((uint)(16 * 1024 * 1024)) /* max 16Mbyte */
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#define CFG_RESET_ADDRESS 0xFFF00100
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#if 0
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#if defined(DEBUG)
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#else
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#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
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#endif
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#else
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#endif
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_OFFSET 0x00F40000
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#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment sector */
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#define CFG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#if defined(CONFIG_WATCHDOG)
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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#else
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
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#endif
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6
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*-----------------------------------------------------------------------
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* PCMCIA config., multi-function pin tri-state
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*/
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#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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*/
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#define CFG_PISCR (PISCR_PS | PISCR_PITF)
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
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*-----------------------------------------------------------------------
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* set the PLL, the low-power modes and the reset control (15-29)
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*/
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#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
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PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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*-----------------------------------------------------------------------
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* Set clock output, timebase and RTC source and divider,
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* power management and some other internal clocks
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*/
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#ifdef CONFIG_100MHz /* for 100 MHz, external bus is half CPU clock */
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#define SCCR_MASK 0
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#define CFG_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \
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SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \
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SCCR_DFLCD000 |SCCR_DFALCD00 | SCCR_EBDF01)
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#else /* up to 50 MHz we use a 1:1 clock */
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#define SCCR_MASK SCCR_EBDF11
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#define CFG_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \
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SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \
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SCCR_DFLCD000 |SCCR_DFALCD00 )
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#endif /* CONFIG_100MHz */
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/*-----------------------------------------------------------------------
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* RCCR - RISC Controller Configuration Register 19-4
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*-----------------------------------------------------------------------
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*/
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/* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */
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#define CFG_RCCR 0x0020
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/*-----------------------------------------------------------------------
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* PCMCIA stuff
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*-----------------------------------------------------------------------
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*/
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#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
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#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
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#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
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#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
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#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
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#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
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#define CFG_PCMCIA_IO_ADDR (0xEC000000)
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#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
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/*-----------------------------------------------------------------------
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* PCMCIA Power Switch
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*
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* The ICU862 uses a TPS2205 PC-Card Power-Interface Switch to
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* control the voltages on the PCMCIA slot which is connected to Port B
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*-----------------------------------------------------------------------
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*/
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/* Output pins */
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#define TPS2205_VCC5 0x00008000 /* PB.16: 5V Voltage Control */
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#define TPS2205_VCC3 0x00004000 /* PB.17: 3V Voltage Control */
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#define TPS2205_VPP_PGM 0x00002000 /* PB.18: PGM Voltage Control */
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#define TPS2205_VPP_VCC 0x00001000 /* PB.19: VPP Voltage Control */
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#define TPS2205_SHDN 0x00000200 /* PB.22: Shutdown */
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#define TPS2205_OUTPUTS ( TPS2205_VCC5 | TPS2205_VCC3 | \
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TPS2205_VPP_PGM | TPS2205_VPP_VCC | \
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TPS2205_SHDN)
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/* Input pins */
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#define TPS2205_OC 0x00000100 /* PB.23: Over-Current */
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#define TPS2205_INPUTS ( TPS2205_OC )
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|
/*-----------------------------------------------------------------------
|
||
|
|
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
|
||
|
|
*-----------------------------------------------------------------------
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
|
||
|
|
|
||
|
|
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
|
||
|
|
#undef CONFIG_IDE_LED /* LED for ide not supported */
|
||
|
|
#undef CONFIG_IDE_RESET /* reset for ide not supported */
|
||
|
|
|
||
|
|
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
|
||
|
|
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
|
||
|
|
|
||
|
|
#define CFG_ATA_IDE0_OFFSET 0x0000
|
||
|
|
|
||
|
|
#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
|
||
|
|
|
||
|
|
/* Offset for data I/O */
|
||
|
|
#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
|
||
|
|
|
||
|
|
/* Offset for normal register accesses */
|
||
|
|
#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
|
||
|
|
|
||
|
|
/* Offset for alternate registers */
|
||
|
|
#define CFG_ATA_ALT_OFFSET 0x0100
|
||
|
|
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------------
|
||
|
|
*
|
||
|
|
*-----------------------------------------------------------------------
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
#define CFG_DER 0
|
||
|
|
|
||
|
|
/* Because of the way the 860 starts up and assigns CS0 the
|
||
|
|
* entire address space, we have to set the memory controller
|
||
|
|
* differently. Normally, you write the option register
|
||
|
|
* first, and then enable the chip select by writing the
|
||
|
|
* base register. For CS0, you must write the base register
|
||
|
|
* first, followed by the option register.
|
||
|
|
*/
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Init Memory Controller:
|
||
|
|
*
|
||
|
|
* BR0 and OR0 (FLASH)
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
|
||
|
|
#define FLASH_BASE1_PRELIM 0x0 /* FLASH bank #1 */
|
||
|
|
|
||
|
|
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
|
||
|
|
#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
|
||
|
|
|
||
|
|
/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
|
||
|
|
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
|
||
|
|
|
||
|
|
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
|
||
|
|
|
||
|
|
#define CFG_OR0_PRELIM 0xFF000954 /* Real values for the board */
|
||
|
|
#define CFG_BR0_PRELIM 0x40000001 /* Real values for the board */
|
||
|
|
|
||
|
|
/*
|
||
|
|
* BR1 and OR1 (SDRAM)
|
||
|
|
*/
|
||
|
|
#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank */
|
||
|
|
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
|
||
|
|
|
||
|
|
#define CFG_OR_TIMING_SDRAM 0x00000800 /* BIH is not set */
|
||
|
|
|
||
|
|
#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM)
|
||
|
|
#define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Memory Periodic Timer Prescaler
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* periodic timer for refresh */
|
||
|
|
#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
|
||
|
|
|
||
|
|
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
|
||
|
|
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
|
||
|
|
#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
|
||
|
|
|
||
|
|
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
|
||
|
|
#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
|
||
|
|
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
|
||
|
|
|
||
|
|
/*
|
||
|
|
* MAMR settings for SDRAM
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* 8 column SDRAM */
|
||
|
|
#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||
|
|
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||
|
|
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
||
|
|
/* 9 column SDRAM */
|
||
|
|
#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||
|
|
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||
|
|
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
||
|
|
|
||
|
|
#define CFG_MAMR 0x13a01114
|
||
|
|
/*
|
||
|
|
* Internal Definitions
|
||
|
|
*
|
||
|
|
* Boot Flags
|
||
|
|
*/
|
||
|
|
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||
|
|
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||
|
|
|
||
|
|
#ifdef CONFIG_MPC860T
|
||
|
|
|
||
|
|
/* Interrupt level assignments.
|
||
|
|
*/
|
||
|
|
#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
|
||
|
|
|
||
|
|
#endif /* CONFIG_MPC860T */
|
||
|
|
|
||
|
|
|
||
|
|
#endif /* __CONFIG_H */
|