411 lines
12 KiB
C
411 lines
12 KiB
C
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/*
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* (C) Copyright 2003
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* MuLogic B.V.
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*
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* (C) Copyright 2002
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* Simple Network Magic Corporation
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* various debug settings */
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#undef CFG_DEVICE_NULLDEV /* null device */
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#undef CONFIG_SILENT_CONSOLE /* silent console */
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#undef CFG_CONSOLE_INFO_QUIET /* silent console ? */
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#undef DEBUG /* debug output code */
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#undef DEBUG_FLASH /* debug flash code */
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#undef FLASH_DEBUG /* debug fash code */
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#undef DEBUG_ENV /* debug environment code */
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#define CFG_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */
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#define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
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#define CONFIG_QS860T 1 /* ...on a QS860T module */
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#define CONFIG_FEC_ENET 1 /* FEC 10/100BaseT ethernet */
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#define CONFIG_MII
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#define FEC_INTERRUPT SIU_LEVEL1
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#undef CONFIG_SCC1_ENET /* SCC1 10BaseT ethernet */
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#define CFG_DISCOVER_PHY
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#undef CONFIG_8xx_CONS_SMC1
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#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC */
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#undef CONFIG_8xx_CONS_NONE
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#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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/* Pass clocks to Linux 2.4.18 in Hz */
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#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */
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#define CONFIG_PREBOOT "echo;" \
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"echo 'Type \"run flash_nfs\" to mount root filesystem over NFS';" \
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"echo"
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#undef CONFIG_BOOTARGS
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/* TODO compare against CADM860 */
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#define CONFIG_BOOTCOMMAND "bootp; " \
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"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
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"bootm"
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#undef CONFIG_STATUS_LED /* Status LED disabled */
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#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
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#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
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CFG_CMD_REGINFO | \
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CFG_CMD_IMMAP | \
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CFG_CMD_ASKENV | \
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CFG_CMD_NET | \
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CFG_CMD_DHCP | \
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CFG_CMD_DATE )
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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/* TODO */
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#if 0
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/* Look at these */
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CONFIG_IPADDR
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CONFIG_SERVERIP
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CONFIG_I2C
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CONFIG_SPI
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#endif
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/*
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* Environment variable storage is in NVRAM
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*/
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#define CFG_ENV_IS_IN_NVRAM 1
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#define CFG_ENV_SIZE 0x00001000 /* We use only the last 4K for PPCBoot */
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#define CFG_ENV_ADDR 0xD100E000
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
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#define CFG_PROMPT_HUSH_PS2 "> "
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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/* TODO - size? */
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#define CFG_MEMTEST_START 0x0400000 /* memtest works */
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*-----------------------------------------------------------------------
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CFG_IMMR 0xF0000000
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0xFFF00000
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#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/* TODO flash parameters */
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/*-----------------------------------------------------------------------
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* FLASH organization for Intel Strataflash
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*/
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#define CFG_FLASH_16BIT 1 /* 16-bit wide flash memory */
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#undef CFG_ENV_IS_IN_FLASH
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#if defined(CONFIG_WATCHDOG)
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#define CFG_SYPCR (0xFFFFFF88 | SYPCR_SWE | SYPCR_SWRI)
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#else
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#define CFG_SYPCR 0xFFFFFF88
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#endif
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6
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*-----------------------------------------------------------------------
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*/
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#define CFG_SIUMCR 0x00620000
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26
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*-----------------------------------------------------------------------
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*/
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#define CFG_TBSCR 0x00C3
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/*-----------------------------------------------------------------------
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* RTCSC - Real-Time Clock Status and Control Register 11-27
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*-----------------------------------------------------------------------
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*/
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#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31
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*-----------------------------------------------------------------------
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*/
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#define CFG_PISCR 0x0082
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
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*-----------------------------------------------------------------------
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*/
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#define CFG_PLPRCR 0x0090D000
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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*-----------------------------------------------------------------------
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*/
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#define SCCR_MASK SCCR_EBDF11
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#define CFG_SCCR 0x02000000
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/*-----------------------------------------------------------------------
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* Debug Enable Register
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* 0x73E67C0F - All interrupts handled by BDM
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* 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM
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*-----------------------------------------------------------------------
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#define CFG_DER 0x73E67C0F
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*/
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#define CFG_DER 0x0082400F
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/*-----------------------------------------------------------------------
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* Memory Controller Initialization Constants
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*-----------------------------------------------------------------------
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*/
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/*
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* BR0 and OR0 (AMD 512K Socketed FLASH)
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* Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation)
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*/
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#define CFG_PRELIM_OR_AM
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#define CFG_OR_TIMING_FLASH
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#define FLASH_BASE0_PRELIM 0xFFF00001
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#define CFG_OR0_PRELIM 0xFFF80D42
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#define CFG_BR0_PRELIM 0xFFF00401
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/*
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* BR1 and OR1 (Intel 8M StrataFLASH)
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* Base address = 0xD000_0000 - 0xD07F_FFFF
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*/
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#define FLASH_BASE1_PRELIM 0xD0000000
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#define CFG_OR1_PRELIM 0xFF800D42
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#define CFG_BR1_PRELIM 0xD0000801
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/* #define CFG_OR1 0xFF800D42 */
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/* #define CFG_BR1 0xD0000801 */
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/*
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* BR2 and OR2 (SDRAM)
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* Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation)
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* Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation)
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* Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation)
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*
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*/
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#define SDRAM_BASE 0x00000000 /* SDRAM bank */
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#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
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/* SDRAM timing */
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#define SDRAM_TIMING 0x00000A00
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/* For boards with 16M of SDRAM */
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#define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */
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#define CFG_16M_MBMR 0x18802114 /* Mem Periodic Timer Prescaler */
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/* For boards with 64M of SDRAM */
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#define SDRAM_64M_MAX_SIZE 0x04000000 /* max 64MB SDRAM */
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/* TODO - determine real value */
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#define CFG_64M_MBMR 0x18802114 /* Mem Period Timer Prescaler */
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#define CFG_OR2 (SDRAM_PRELIM_OR_AM | SDRAM_TIMING)
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#define CFG_BR2 (SDRAM_BASE | 0x000000C1)
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/*
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* BR3 and OR3 (NVRAM, Sipex, NAND Flash)
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* Base address = 0xD100_0000 - 0xD100_FFFF (64K NVRAM)
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* Base address = 0xD108_0000 - 0xD108_0000 (Sipex chip ctl register)
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* Base address = 0xD110_0000 - 0xD110_0000 (NAND ctl register)
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* Base address = 0xD138_0000 - 0xD138_0000 (LED ctl register)
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*
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*/
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#define CFG_OR3_PRELIM 0xFFC00DF6
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#define CFG_BR3_PRELIM 0xD1000401
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/* #define CFG_OR3 0xFFC00DF6 */
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/* #define CFG_BR3 0xD1000401 */
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/*
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* BR4 and OR4 (Unused)
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* Base address = 0xE000_0000 - 0xE3FF_FFFF
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*
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*/
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#define CFG_OR4_PRELIM 0xFF000000
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#define CFG_BR4_PRELIM 0xE0000000
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/* #define CFG_OR4 0xFF000000 */
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/* #define CFG_BR4 0xE0000000 */
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/*
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* BR5 and OR5 (Expansion bus)
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* Base address = 0xE400_0000 - 0xE7FF_FFFF
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*
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*/
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#define CFG_OR5_PRELIM 0xFF000000
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#define CFG_BR5_PRELIM 0xE4000000
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/* #define CFG_OR5 0xFF000000 */
|
||
|
|
/* #define CFG_BR5 0xE4000000 */
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* BR6 and OR6 (Expansion bus)
|
||
|
|
* Base address = 0xE800_0000 - 0xEBFF_FFFF
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define CFG_OR6_PRELIM 0xFF000000
|
||
|
|
#define CFG_BR6_PRELIM 0xE8000000
|
||
|
|
/* #define CFG_OR6 0xFF000000 */
|
||
|
|
/* #define CFG_BR6 0xE8000000 */
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* BR7 and OR7 (Expansion bus)
|
||
|
|
* Base address = 0xEC00_0000 - 0xEFFF_FFFF
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define CFG_OR7_PRELIM 0xFF000000
|
||
|
|
#define CFG_BR7_PRELIM 0xE8000000
|
||
|
|
/* #define CFG_OR7 0xFF000000 */
|
||
|
|
/* #define CFG_BR7 0xE8000000 */
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Internal Definitions
|
||
|
|
*
|
||
|
|
* Boot Flags
|
||
|
|
*/
|
||
|
|
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||
|
|
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Sanity checks
|
||
|
|
*/
|
||
|
|
#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
|
||
|
|
#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* __CONFIG_H */
|