451 lines
15 KiB
C
451 lines
15 KiB
C
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/*
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* (C) Copyright 2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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* Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
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* U-BOOT port on RPXlite board
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*/
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/*
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* Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
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* U-BOOT port on RPXlite DW version board--RPXlite_DW
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* June 8 ,2004
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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/* #define DEBUG 1 */
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/* #ifdef DEPLOYMENT 1 */
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#undef CONFIG_MPC860
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#define CONFIG_MPC823 1 /* This is a MPC823e CPU. */
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#define CONFIG_RPXLITE 1 /* RPXlite DW version board */
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#ifdef CONFIG_LCD /* with LCD controller ? */
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#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
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#endif
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#undef CONFIG_8xx_CONS_SMC2
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#undef CONFIG_8xx_CONS_NONE
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#define CONFIG_BAUDRATE 9600 /* console default baudrate = 9600bps */
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#ifdef DEBUG
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 6 /* autoboot after 6 seconds */
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#ifdef DEPLOYMENT
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#define CONFIG_BOOT_RETRY_TIME -1
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#define CONFIG_AUTOBOOT_KEYED
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#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds (stop with 'st')...\n"
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#define CONFIG_AUTOBOOT_STOP_STR "st"
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#define CONFIG_ZERO_BOOTDELAY_CHECK
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#define CONFIG_RESET_TO_RETRY 1
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#define CONFIG_BOOT_RETRY_MIN 1
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#endif /* DEPLOYMENT */
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#endif /* DEBUG */
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/* pre-boot commands */
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#define CONFIG_PREBOOT "setenv stdout serial;setenv stdin serial"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"nfsargs=setenv bootargs console=tty0 console=ttyS0,9600 " \
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"root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs console=tty0 root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"flash_nfs=run nfsargs addip;" \
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"bootm ${kernel_addr}\0" \
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"flash_self=run ramargs addip;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
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"gatewayip=172.16.115.254\0" \
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"netmask=255.255.255.0\0" \
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"kernel_addr=ff040000\0" \
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"ramdisk_addr=ff200000\0" \
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"ku=era ${kernel_addr} ff1fffff;cp.b 100000 ${kernel_addr} " \
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"${filesize};md ${kernel_addr};" \
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"echo kernel updating finished\0" \
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"uu=protect off 1:0-4;era 1:0-4;cp.b 100000 ff000000 " \
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"${filesize};md ff000000;" \
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"echo u-boot updating finished\0" \
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"eu=protect off 1:6;era 1:6;reset\0" \
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"lcd=setenv stdout lcd;setenv stdin lcd\0" \
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"ser=setenv stdout serial;setenv stdin serial\0" \
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"verify=no"
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#define CONFIG_BOOTCOMMAND "run flash_self"
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#undef CONFIG_STATUS_LED /* disturbs display. Status LED disabled. */
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#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "u-boot>" /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0040000 /* memtest works on */
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#define CFG_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CFG_IMMR 0xFA200000
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0xFF000000
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#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#else
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#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
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#endif
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#define CFG_MONITOR_BASE 0xFF000000
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#ifdef CFG_ENV_IS_IN_NVRAM
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#define CFG_ENV_ADDR 0xFA000100
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#define CFG_ENV_SIZE 0x1000
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#else
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#define CFG_ENV_IS_IN_FLASH
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#define CFG_ENV_OFFSET 0x30000 /* Offset of Environment Sector */
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#define CFG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */
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#endif /* CFG_ENV_IS_IN_NVRAM */
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#define CFG_RESET_ADDRESS ((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res)))
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 32-bit 12-35
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#if defined(CONFIG_WATCHDOG)
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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#else
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#define CFG_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
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#endif /* We can get SYPCR: 0xFFFF0689. */
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 32-bit 12-30
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*-----------------------------------------------------------------------
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* PCMCIA config., multi-function pin tri-state
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*/
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#define CFG_SIUMCR (SIUMCR_MLRC10) /* SIUMCR:0x00000800 */
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/*---------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 16-bit 12-16
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*---------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
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/* TBSCR: 0x00C3 [SAM] */
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/*-----------------------------------------------------------------------
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* RTCSC - Real-Time Clock Status and Control Register 16-bit 12-18
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*-----------------------------------------------------------------------
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* [RTC enabled but not stopped on FRZ]
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*/
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#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE) /* RTCSC:0x00C1 */
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 16-bit 12-23
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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* [Periodic timer enabled,Periodic timer interrupt disable. ]
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*/
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#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) /* PISCR:0x0083 */
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 32-bit 5-7
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*-----------------------------------------------------------------------
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* Reset PLL lock status sticky bit, timer expired status bit and timer
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* interrupt status bit
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*/
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/* up to 64 MHz we use a 1:2 clock */
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#if defined(RPXlite_64MHz)
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#define CFG_PLPRCR ( (7 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) /*PLPRCR: 0x00700000. */
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#else
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#define CFG_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
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#endif
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 5-3
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*-----------------------------------------------------------------------
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* Set clock output, timebase and RTC source and divider,
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* power management and some other internal clocks
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*/
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#define SCCR_MASK SCCR_EBDF00
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/* Up to 48MHz system clock, we use 1:1 SYSTEM/BUS ratio */
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#if defined(RPXlite_64MHz)
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#define CFG_SCCR ( SCCR_TBS | SCCR_EBDF01 ) /* %%%SCCR:0x02020000 */
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#else
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#define CFG_SCCR ( SCCR_TBS | SCCR_EBDF00 ) /* %%%SCCR:0x02000000 */
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#endif
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/*-----------------------------------------------------------------------
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* PCMCIA stuff
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*-----------------------------------------------------------------------
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*/
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#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
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#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
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#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
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#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
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#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
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#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
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#define CFG_PCMCIA_IO_ADDR (0xEC000000)
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#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
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/*-----------------------------------------------------------------------
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* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
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#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
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#undef CONFIG_IDE_LED /* LED for ide not supported */
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#undef CONFIG_IDE_RESET /* reset for ide not supported */
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#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
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#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
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#define CFG_ATA_IDE0_OFFSET 0x0000
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#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
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/* Offset for data I/O */
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#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
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/* Offset for normal register accesses */
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#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
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/* Offset for alternate registers */
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#define CFG_ATA_ALT_OFFSET 0x0100
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#define CFG_DER 0
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/*
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* Init Memory Controller:
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*
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* BR0 and OR0 (FLASH)
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*/
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#define FLASH_BASE_PRELIM 0xFC000000 /* FLASH base */
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#define CFG_PRELIM_OR_AM 0xFC000000 /* OR addr mask */
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/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 8, ETHR = 0, BIH = 1 */
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#define CFG_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_BI)
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#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
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#define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
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/*
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* BR1 and OR1 (SDRAM)
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*
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*/
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#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
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#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB in system */
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/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
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#define CFG_OR_TIMING_SDRAM 0x00000E00
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#define CFG_OR_AM_SDRAM (-(SDRAM_MAX_SIZE & OR_AM_MSK))
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#define CFG_OR1_PRELIM ( CFG_OR_AM_SDRAM | CFG_OR_TIMING_SDRAM )
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#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
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/* RPXlite mem setting */
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#define CFG_BR3_PRELIM 0xFA400001 /* BCSR */
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#define CFG_OR3_PRELIM 0xFF7F8900
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#define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
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#define CFG_OR4_PRELIM 0xFFFE0040
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/*
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* Memory Periodic Timer Prescaler
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*/
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/* periodic timer for refresh */
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#if defined(RPXlite_64MHz)
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#define CFG_MAMR_PTA 32
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#else
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#define CFG_MAMR_PTA 20
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#endif
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||
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/*
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||
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* Refresh clock Prescalar
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||
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*/
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||
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#define CFG_MPTPR MPTPR_PTP_DIV2
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||
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||
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/*
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||
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* MAMR settings for SDRAM
|
||
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*/
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||
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/* 9 column SDRAM */
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#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
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||
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MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10)
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||
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/* CFG_MAMR_9COL:0x20904000 @ 64MHz */
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||
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|
||
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/*
|
||
|
|
* Internal Definitions
|
||
|
|
*
|
||
|
|
* Boot Flags
|
||
|
|
*/
|
||
|
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||
|
|
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||
|
|
|
||
|
|
/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
|
||
|
|
/* Configuration variable added by yooth. */
|
||
|
|
/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
|
||
|
|
/*
|
||
|
|
* BCSRx
|
||
|
|
*
|
||
|
|
* Board Status and Control Registers
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
#define BCSR0 0xFA400000
|
||
|
|
#define BCSR1 0xFA400001
|
||
|
|
#define BCSR2 0xFA400002
|
||
|
|
#define BCSR3 0xFA400003
|
||
|
|
|
||
|
|
#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
|
||
|
|
#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
|
||
|
|
#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
|
||
|
|
#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
|
||
|
|
#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
|
||
|
|
#define BCSR0_COLTEST 0x20
|
||
|
|
#define BCSR0_ETHLPBK 0x40
|
||
|
|
#define BCSR0_ETHEN 0x80
|
||
|
|
|
||
|
|
#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
|
||
|
|
#define BCSR1_PCVCTL6 0x02
|
||
|
|
#define BCSR1_PCVCTL5 0x04
|
||
|
|
#define BCSR1_PCVCTL4 0x08
|
||
|
|
#define BCSR1_IPB5SEL 0x10
|
||
|
|
|
||
|
|
#define BCSR1_SMC1CTS 0x40 /* Added by SAM. */
|
||
|
|
#define BCSR1_SMC1TRS 0x80 /* Added by SAM. */
|
||
|
|
|
||
|
|
#define BCSR2_ENRTCIRQ 0x01 /* Added by SAM. */
|
||
|
|
#define BCSR2_ENBRG1 0x04 /* Added by SAM. */
|
||
|
|
|
||
|
|
#define BCSR2_ENPA5HDR 0x08 /* USB Control */
|
||
|
|
#define BCSR2_ENUSBCLK 0x10
|
||
|
|
#define BCSR2_USBPWREN 0x20
|
||
|
|
#define BCSR2_USBSPD 0x40
|
||
|
|
#define BCSR2_USBSUSP 0x80
|
||
|
|
|
||
|
|
#define BCSR3_BWKAPWR 0x01 /* Changed by SAM. Backup battery situation */
|
||
|
|
#define BCSR3_IRQRTC 0x02 /* Changed by SAM. NVRAM Battery */
|
||
|
|
#define BCSR3_RDY_BSY 0x04 /* Changed by SAM. Flash Operation */
|
||
|
|
#define BCSR3_MPLX_LIN 0x08 /* Changed by SAM. Linear or Multiplexed address Mode */
|
||
|
|
|
||
|
|
#define BCSR3_D27 0x10 /* Dip Switch settings */
|
||
|
|
#define BCSR3_D26 0x20
|
||
|
|
#define BCSR3_D25 0x40
|
||
|
|
#define BCSR3_D24 0x80
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Environment setting
|
||
|
|
*/
|
||
|
|
#define CONFIG_ETHADDR 00:10:EC:00:37:5B
|
||
|
|
#define CONFIG_IPADDR 172.16.115.7
|
||
|
|
#define CONFIG_SERVERIP 172.16.115.6
|
||
|
|
#define CONFIG_ROOTPATH /workspace/myfilesystem/target/
|
||
|
|
#define CONFIG_BOOTFILE uImage.rpxusb
|
||
|
|
|
||
|
|
#endif /* __CONFIG_H */
|