505 lines
16 KiB
C
505 lines
16 KiB
C
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*****************************************************************************
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*
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* These settings must match the way _your_ board is set up
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*
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*****************************************************************************/
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/* for the AY-Revision which does not use the HRCW */
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#define CFG_DEFAULT_IMMR 0x00010000
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/* What is the oscillator's (UX2) frequency in Hz? */
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#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
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/* How is switch S2 set? We really only want the MODCK[1-3] bits, so
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* only the 3 least significant bits are important.
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*/
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#define CFG_SBC_S2 0x04
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/* What should MODCK_H be? It is dependent on the oscillator
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* frequency, MODCK[1-3], and desired CPM and core frequencies.
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* Some example values (all frequencies are in MHz):
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*
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* MODCK_H MODCK[1-3] Osc CPM Core
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* 0x2 0x2 33 133 133
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* 0x2 0x4 33 133 200
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* 0x5 0x5 66 133 133
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* 0x5 0x7 66 133 200
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*/
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#define CFG_SBC_MODCK_H 0x06
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#define CFG_SBC_BOOT_LOW 1 /* only for HRCW */
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#undef CFG_SBC_BOOT_LOW
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/* What should the base address of the main FLASH be and how big is
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* it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk
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* The main FLASH is whichever is connected to *CS0. U-Boot expects
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* this to be the SIMM.
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*/
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#define CFG_FLASH0_BASE 0x80000000
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#define CFG_FLASH0_SIZE 16
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/* What should the base address of the secondary FLASH be and how big
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* is it (in Mbytes)? The secondary FLASH is whichever is connected
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* to *CS6. U-Boot expects this to be the on board FLASH. If you don't
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* want it enabled, don't define these constants.
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*/
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#define CFG_FLASH1_BASE 0
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#define CFG_FLASH1_SIZE 0
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#undef CFG_FLASH1_BASE
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#undef CFG_FLASH1_SIZE
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/* What should be the base address of SDRAM DIMM and how big is
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* it (in Mbytes)?
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*/
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#define CFG_SDRAM0_BASE 0x00000000
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#define CFG_SDRAM0_SIZE 64
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/* What should be the base address of SDRAM DIMM and how big is
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* it (in Mbytes)?
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*/
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#define CFG_SDRAM1_BASE 0x04000000
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#define CFG_SDRAM1_SIZE 32
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/* What should be the base address of the LEDs and switch S0?
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* If you don't want them enabled, don't define this.
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*/
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#define CFG_LED_BASE 0x00000000
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/*
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* select serial console configuration
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*
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* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
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* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
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* for SCC).
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*
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* if CONFIG_CONS_NONE is defined, then the serial console routines must
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* defined elsewhere.
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*/
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#define CONFIG_CONS_ON_SMC /* define if console on SMC */
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#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
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#undef CONFIG_CONS_NONE /* define if console on neither */
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#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
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/*
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* select ethernet configuration
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*
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* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
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* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
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* for FCC)
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*
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* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
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* defined elsewhere (as for the console), or CFG_CMD_NET must be removed
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* from CONFIG_COMMANDS to remove support for networking.
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*/
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#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
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#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
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#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
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#define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */
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#if ( CONFIG_ETHER_INDEX == 3 )
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/*
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* - Rx-CLK is CLK15
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* - Tx-CLK is CLK16
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* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
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* - Enable Half Duplex in FSMR
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*/
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# define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
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# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
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# define CFG_CPMFCR_RAMTYPE 0
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/*#define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) */
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# define CFG_FCC_PSMR 0
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#else /* CONFIG_ETHER_INDEX */
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# error "on RPX Super ethernet must be FCC3"
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#endif /* CONFIG_ETHER_INDEX */
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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/* Define this to reserve an entire FLASH sector (256 KB) for
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* environment variables. Otherwise, the environment will be
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* put in the same sector as U-Boot, and changing variables
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* will erase U-Boot temporarily
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*/
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#define CFG_ENV_IN_OWN_SECT
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/* Define to allow the user to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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/* What should the console's baud rate be? */
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#define CONFIG_BAUDRATE 115200
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/* Ethernet MAC address */
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#define CONFIG_ETHADDR 08:00:22:50:70:63
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#define CONFIG_IPADDR 192.168.1.99
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#define CONFIG_SERVERIP 192.168.1.3
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/* Set to a positive value to delay for running BOOTCOMMAND */
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#define CONFIG_BOOTDELAY -1
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/* undef this to save memory */
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#define CFG_LONGHELP
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/* Monitor Command Prompt */
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#define CFG_PROMPT "=> "
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/* What U-Boot subsytems do you want enabled? */
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
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CFG_CMD_IMMAP | \
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CFG_CMD_ASKENV | \
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CFG_CMD_ECHO | \
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CFG_CMD_I2C | \
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CFG_CMD_REGINFO & \
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~CFG_CMD_KGDB )
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/* Where do the internal registers live? */
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#define CFG_IMMR 0xF0000000
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/* Where do the on board registers (CS4) live? */
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#define CFG_REGS_BASE 0xFA000000
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/*****************************************************************************
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*
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* You should not have to modify any of the following settings
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*
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*****************************************************************************/
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#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
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#define CONFIG_RPXSUPER 1 /* on an Embedded Planet RPX Super Board */
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#define CONFIG_CPM2 1 /* Has a CPM2 */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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/*
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* Miscellaneous configurable options
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*/
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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/* Print Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
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#define CFG_MAXARGS 8 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x04000000 /* memtest works on */
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#define CFG_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */
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#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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/* valid baudrates */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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#define CFG_FLASH_BASE CFG_FLASH0_BASE
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#define CFG_SDRAM_BASE CFG_SDRAM0_BASE
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/*-----------------------------------------------------------------------
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* Hard Reset Configuration Words
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*/
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#if defined(CFG_SBC_BOOT_LOW)
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# define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
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#else
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# define CFG_SBC_HRCW_BOOT_FLAGS (0)
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#endif /* defined(CFG_SBC_BOOT_LOW) */
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/* get the HRCW ISB field from CFG_IMMR */
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#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\
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((CFG_IMMR & 0x01000000) >> 7) |\
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((CFG_IMMR & 0x00100000) >> 4) )
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#define CFG_HRCW_MASTER (HRCW_BPS11 |\
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HRCW_DPPC11 |\
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CFG_SBC_HRCW_IMMR |\
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HRCW_MMR00 |\
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HRCW_LBPC11 |\
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HRCW_APPC10 |\
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HRCW_CS10PC00 |\
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(CFG_SBC_MODCK_H & HRCW_MODCK_H1111) |\
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CFG_SBC_HRCW_BOOT_FLAGS)
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/* no slaves */
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#define CFG_HRCW_SLAVE1 0
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#define CFG_HRCW_SLAVE2 0
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#define CFG_HRCW_SLAVE3 0
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#define CFG_HRCW_SLAVE4 0
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#define CFG_HRCW_SLAVE5 0
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#define CFG_HRCW_SLAVE6 0
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#define CFG_HRCW_SLAVE7 0
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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* Note also that the logic that sets CFG_RAMBOOT is platform dependent.
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*/
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#define CFG_MONITOR_BASE (CFG_FLASH0_BASE + 0x00F00000)
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#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
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# define CFG_RAMBOOT
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#endif
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
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#ifndef CFG_RAMBOOT
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# define CFG_ENV_IS_IN_FLASH 1
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# ifdef CFG_ENV_IN_OWN_SECT
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# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
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# define CFG_ENV_SECT_SIZE 0x40000
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# else
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# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
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# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
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# define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
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# endif /* CFG_ENV_IN_OWN_SECT */
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#else
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# define CFG_ENV_IS_IN_NVRAM 1
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# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
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# define CFG_ENV_SIZE 0x200
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#endif /* CFG_RAMBOOT */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* HIDx - Hardware Implementation-dependent Registers 2-11
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*-----------------------------------------------------------------------
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* HID0 also contains cache control - initially enable both caches and
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* invalidate contents, then the final state leaves only the instruction
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* cache enabled. Note that Power-On and Hard reset invalidate the caches,
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* but Soft reset does not.
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*
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* HID1 has only read-only information - nothing to set.
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*/
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#define CFG_HID0_INIT (/*HID0_ICE |*/\
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/*HID0_DCE |*/\
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HID0_ICFI |\
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HID0_DCI |\
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HID0_IFEM |\
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HID0_ABE)
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#define CFG_HID0_FINAL (/*HID0_ICE |*/\
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HID0_IFEM |\
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HID0_ABE |\
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HID0_EMCP)
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#define CFG_HID2 0
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/*-----------------------------------------------------------------------
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* RMR - Reset Mode Register
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*-----------------------------------------------------------------------
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*/
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#define CFG_RMR 0
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/*-----------------------------------------------------------------------
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* BCR - Bus Configuration 4-25
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*-----------------------------------------------------------------------
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*/
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#define CFG_BCR (BCR_EBM |\
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||
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BCR_PLDP |\
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||
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BCR_EAV |\
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||
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BCR_NPQM0)
|
||
|
|
|
||
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/*-----------------------------------------------------------------------
|
||
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|
* SIUMCR - SIU Module Configuration 4-31
|
||
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|
*-----------------------------------------------------------------------
|
||
|
|
*/
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||
|
|
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||
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#define CFG_SIUMCR (SIUMCR_L2CPC01 |\
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||
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SIUMCR_APPC10 |\
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||
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SIUMCR_CS10PC01)
|
||
|
|
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------------
|
||
|
|
* SYPCR - System Protection Control 11-9
|
||
|
|
* SYPCR can only be written once after reset!
|
||
|
|
*-----------------------------------------------------------------------
|
||
|
|
* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
|
||
|
|
*/
|
||
|
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#define CFG_SYPCR (SYPCR_SWTC |\
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||
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SYPCR_BMT |\
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||
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SYPCR_PBME |\
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||
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SYPCR_LBME |\
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||
|
|
SYPCR_SWRI |\
|
||
|
|
SYPCR_SWP)
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------------
|
||
|
|
* TMCNTSC - Time Counter Status and Control 4-40
|
||
|
|
*-----------------------------------------------------------------------
|
||
|
|
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
|
||
|
|
* and enable Time Counter
|
||
|
|
*/
|
||
|
|
#define CFG_TMCNTSC (TMCNTSC_SEC |\
|
||
|
|
TMCNTSC_ALR |\
|
||
|
|
TMCNTSC_TCF |\
|
||
|
|
TMCNTSC_TCE)
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------------
|
||
|
|
* PISCR - Periodic Interrupt Status and Control 4-42
|
||
|
|
*-----------------------------------------------------------------------
|
||
|
|
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
|
||
|
|
* Periodic timer
|
||
|
|
*/
|
||
|
|
#define CFG_PISCR (PISCR_PS |\
|
||
|
|
PISCR_PTF |\
|
||
|
|
PISCR_PTE)
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------------
|
||
|
|
* SCCR - System Clock Control 9-8
|
||
|
|
*-----------------------------------------------------------------------
|
||
|
|
*/
|
||
|
|
#define CFG_SCCR (SCCR_DFBRG01)
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------------
|
||
|
|
* RCCR - RISC Controller Configuration 13-7
|
||
|
|
*-----------------------------------------------------------------------
|
||
|
|
*/
|
||
|
|
#define CFG_RCCR 0
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Init Memory Controller:
|
||
|
|
*
|
||
|
|
* Bank Bus Machine PortSz Device
|
||
|
|
* ---- --- ------- ------ ------
|
||
|
|
* 0 60x GPCM 64 bit FLASH (BGA - 16MB AMD AM29DL323DB90)
|
||
|
|
* 1 60x SDRAM 64 bit SDRAM (BGA - 64MB Hitachi HM5225325FBP-B60)
|
||
|
|
* 2 Local SDRAM 32 bit SDRAM (BGA - 32MB Hitachi HM5225325FBP-B60)
|
||
|
|
* 3 unused
|
||
|
|
* 4 60x GPCM 8 bit Board Regs, LEDs, switches
|
||
|
|
* 5 unused
|
||
|
|
* 6 unused
|
||
|
|
* 7 unused
|
||
|
|
* 8 PCMCIA
|
||
|
|
* 9 unused
|
||
|
|
* 10 unused
|
||
|
|
* 11 unused
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* Bank 0 - FLASH
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
|
||
|
|
BRx_PS_64 |\
|
||
|
|
BRx_DECC_NONE |\
|
||
|
|
BRx_MS_GPCM_P |\
|
||
|
|
BRx_V)
|
||
|
|
|
||
|
|
#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\
|
||
|
|
ORxG_CSNT |\
|
||
|
|
ORxG_ACS_DIV1 |\
|
||
|
|
ORxG_SCY_6_CLK |\
|
||
|
|
ORxG_EHTR)
|
||
|
|
|
||
|
|
/* Bank 1 - SDRAM
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
#define CFG_BR1_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
|
||
|
|
BRx_PS_64 |\
|
||
|
|
BRx_MS_SDRAM_P |\
|
||
|
|
BRx_V)
|
||
|
|
|
||
|
|
#define CFG_OR1_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
|
||
|
|
ORxS_BPD_4 |\
|
||
|
|
ORxS_ROWST_PBI0_A8 |\
|
||
|
|
ORxS_NUMR_12 |\
|
||
|
|
ORxS_IBID)
|
||
|
|
|
||
|
|
#define CFG_PSDMR 0x014DA412
|
||
|
|
#define CFG_PSRT 0x79
|
||
|
|
|
||
|
|
|
||
|
|
/* Bank 2 - SDRAM
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
#define CFG_BR2_PRELIM ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
|
||
|
|
BRx_PS_32 |\
|
||
|
|
BRx_MS_SDRAM_L |\
|
||
|
|
BRx_V)
|
||
|
|
|
||
|
|
#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM1_SIZE) |\
|
||
|
|
ORxS_BPD_4 |\
|
||
|
|
ORxS_ROWST_PBI0_A9 |\
|
||
|
|
ORxS_NUMR_12)
|
||
|
|
|
||
|
|
#define CFG_LSDMR 0x0169A512
|
||
|
|
#define CFG_LSRT 0x79
|
||
|
|
|
||
|
|
#define CFG_MPTPR (0x0800 & MPTPR_PTP_MSK)
|
||
|
|
|
||
|
|
/* Bank 4 - On board registers
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
#define CFG_BR4_PRELIM ((CFG_REGS_BASE & BRx_BA_MSK) |\
|
||
|
|
BRx_PS_8 |\
|
||
|
|
BRx_MS_GPCM_P |\
|
||
|
|
BRx_V)
|
||
|
|
|
||
|
|
#define CFG_OR4_PRELIM (ORxG_AM_MSK |\
|
||
|
|
ORxG_CSNT |\
|
||
|
|
ORxG_ACS_DIV1 |\
|
||
|
|
ORxG_SCY_5_CLK |\
|
||
|
|
ORxG_TRLX)
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Internal Definitions
|
||
|
|
*
|
||
|
|
* Boot Flags
|
||
|
|
*/
|
||
|
|
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||
|
|
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||
|
|
|
||
|
|
#endif /* __CONFIG_H */
|