433 lines
16 KiB
C
433 lines
16 KiB
C
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/*
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* (C) Copyright 2000-2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_405EP 1 /* This is a PPC405 CPU */
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#define CONFIG_4xx 1 /* ...member of PPC4xx family */
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#define CONFIG_BUBINGA 1 /* ...on a BUBINGA board */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
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#define CONFIG_NO_SERIAL_EEPROM
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/*#undef CONFIG_NO_SERIAL_EEPROM*/
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/*----------------------------------------------------------------------------*/
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#ifdef CONFIG_NO_SERIAL_EEPROM
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/*
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!-------------------------------------------------------------------------------
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! Defines for entry options.
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! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
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! are plugged in the board will be utilized as non-ECC DIMMs.
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!-------------------------------------------------------------------------------
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*/
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#define AUTO_MEMORY_CONFIG
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#define DIMM_READ_ADDR 0xAB
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#define DIMM_WRITE_ADDR 0xAA
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/*
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!-------------------------------------------------------------------------------
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! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
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! assuming a 33MHz input clock to the 405EP from the C9531.
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!-------------------------------------------------------------------------------
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*/
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#define PLLMR0_DEFAULT PLLMR0_266_133_66
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#define PLLMR1_DEFAULT PLLMR1_266_133_66
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#endif
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/*----------------------------------------------------------------------------*/
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/*
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* Define here the location of the environment variables (FLASH or NVRAM).
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* Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
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* supported for backward compatibility.
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*/
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#if 1
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#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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#else
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#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
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#endif
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"hostname=bubinga\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
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"flash_nfs=run nfsargs addip addtty;" \
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"bootm ${kernel_addr}\0" \
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"flash_self=run ramargs addip addtty;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
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"bootm\0" \
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"rootpath=/opt/eldk/ppc_4xx\0" \
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"bootfile=/tftpboot/bubinga/uImage\0" \
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"kernel_addr=fff80000\0" \
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"ramdisk_addr=fff90000\0" \
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"load=tftp 100000 /tftpboot/bubinga/u-boot.bin\0" \
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"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
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"cp.b 100000 fffc0000 40000;" \
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"setenv filesize;saveenv\0" \
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"upd=run load;run update\0" \
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""
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#define CONFIG_BOOTCOMMAND "run net_nfs"
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#endif
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 1 /* PHY address */
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#define CONFIG_HAS_ETH1
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#define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */
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#define CONFIG_NET_MULTI 1
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#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
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#define CONFIG_NETCONSOLE /* include NetConsole support */
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#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
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CFG_CMD_ASKENV | \
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CFG_CMD_CACHE | \
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CFG_CMD_DATE | \
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CFG_CMD_DHCP | \
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CFG_CMD_EEPROM | \
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CFG_CMD_ELF | \
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CFG_CMD_I2C | \
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CFG_CMD_IRQ | \
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CFG_CMD_MII | \
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CFG_CMD_NET | \
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CFG_CMD_PCI | \
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CFG_CMD_PING | \
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CFG_CMD_REGINFO | \
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CFG_CMD_SDRAM | \
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CFG_CMD_SNTP )
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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/*
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* If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
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* If CFG_405_UART_ERRATA_59, then UART divisor is 31.
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* Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
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* The Linux BASE_BAUD define should match this configuration.
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* baseBaud = cpuClock/(uartDivisor*16)
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* If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
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* set Linux BASE_BAUD to 403200.
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*/
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#undef CONFIG_SERIAL_SOFTWARE_FIFO
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#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
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#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
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#define CFG_BASE_BAUD 691200
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/* The following table includes the supported baudrates */
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
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#define CONFIG_LOOPW 1 /* enable loopw command */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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/*-----------------------------------------------------------------------
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* I2C stuff
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
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#if (CONFIG_COMMANDS & CFG_CMD_EEPROM)
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#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */
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#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
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#endif
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
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#define PCI_HOST_FORCE 1 /* configure as pci host */
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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/* resource configuration */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
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#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
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#define CFG_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */
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#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
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#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
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#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
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#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
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#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
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#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
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/*-----------------------------------------------------------------------
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* External peripheral base address
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*-----------------------------------------------------------------------
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*/
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#define CFG_KEY_REG_BASE_ADDR 0xF0100000
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#define CFG_IR_REG_BASE_ADDR 0xF0200000
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#define CFG_FPGA_REG_BASE_ADDR 0xF0300000
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_SRAM_BASE 0xFFF00000
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#define CFG_FLASH_BASE 0xFFF80000
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
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#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
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#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_ADDR0 0x5555
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#define CFG_FLASH_ADDR1 0x2aaa
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#define CFG_FLASH_WORD_SIZE unsigned char
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#ifdef CFG_ENV_IS_IN_FLASH
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#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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#endif /* CFG_ENV_IS_IN_FLASH */
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/*-----------------------------------------------------------------------
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* NVRAM organization
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*/
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#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
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#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
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#ifdef CFG_ENV_IS_IN_NVRAM
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#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
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#define CFG_ENV_ADDR \
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(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
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#endif
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_DCACHE_SIZE 16384 /* For AMCC 405EP CPU */
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#define CFG_CACHELINE_SIZE 32 /* ... */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*
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* Init Memory Controller:
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*
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* BR0/1 and OR0/1 (FLASH)
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*/
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#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
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#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in data cache)
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*/
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/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
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#define CFG_TEMP_STACK_OCM 1
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/* On Chip Memory location */
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#define CFG_OCM_DATA_ADDR 0xF8000000
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#define CFG_OCM_DATA_SIZE 0x1000
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#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
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#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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||
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/*-----------------------------------------------------------------------
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* External Bus Controller (EBC) Setup
|
||
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*/
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/* Memory Bank 0 (Flash/SRAM) initialization */
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#define CFG_EBC_PB0AP 0x04006000
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#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
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||
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|
/* Memory Bank 1 (NVRAM/RTC) initialization */
|
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#define CFG_EBC_PB1AP 0x04041000
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#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
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|
||
|
|
/* Memory Bank 2 (not used) initialization */
|
||
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|
#define CFG_EBC_PB2AP 0x00000000
|
||
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|
#define CFG_EBC_PB2CR 0x00000000
|
||
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|
|
||
|
|
/* Memory Bank 2 (not used) initialization */
|
||
|
|
#define CFG_EBC_PB3AP 0x00000000
|
||
|
|
#define CFG_EBC_PB3CR 0x00000000
|
||
|
|
|
||
|
|
/* Memory Bank 4 (FPGA regs) initialization */
|
||
|
|
#define CFG_EBC_PB4AP 0x01815000
|
||
|
|
#define CFG_EBC_PB4CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------------
|
||
|
|
* Definitions for Serial Presence Detect EEPROM address
|
||
|
|
* (to get SDRAM settings)
|
||
|
|
*/
|
||
|
|
#define SPD_EEPROM_ADDRESS 0x55
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------------
|
||
|
|
* Definitions for GPIO setup (PPC405EP specific)
|
||
|
|
*
|
||
|
|
* GPIO0[0] - External Bus Controller BLAST output
|
||
|
|
* GPIO0[1-9] - Instruction trace outputs
|
||
|
|
* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
|
||
|
|
* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
|
||
|
|
* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
|
||
|
|
* GPIO0[24-27] - UART0 control signal inputs/outputs
|
||
|
|
* GPIO0[28-29] - UART1 data signal input/output
|
||
|
|
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
|
||
|
|
*/
|
||
|
|
#define CFG_GPIO0_OSRH 0x55555555
|
||
|
|
#define CFG_GPIO0_OSRL 0x40000110
|
||
|
|
#define CFG_GPIO0_ISR1H 0x00000000
|
||
|
|
#define CFG_GPIO0_ISR1L 0x15555445
|
||
|
|
#define CFG_GPIO0_TSRH 0x00000000
|
||
|
|
#define CFG_GPIO0_TSRL 0x00000000
|
||
|
|
#define CFG_GPIO0_TCR 0xFFFF8014
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------------
|
||
|
|
* Some BUBINGA stuff...
|
||
|
|
*/
|
||
|
|
#define NVRAM_BASE 0xF0000000
|
||
|
|
#define FPGA_REG0 0xF0300000 /* FPGA Reg 0 */
|
||
|
|
#define FPGA_REG1 0xF0300001 /* FPGA Reg 1 */
|
||
|
|
#define NVRVFY1 0x4f532d4f /* used to determine if state data in */
|
||
|
|
#define NVRVFY2 0x50454e00 /* NVRAM initialized (ascii for OS-OPEN)*/
|
||
|
|
|
||
|
|
#define FPGA_REG0_F_RANGE 0x80 /* SDRAM PLL freq range */
|
||
|
|
#define FPGA_REG0_EXT_INT_DIS 0x20 /* External interface disable */
|
||
|
|
#define FPGA_REG0_LED_MASK 0x07 /* Board LEDs DS9, DS10, and DS11 */
|
||
|
|
#define FPGA_REG0_LED0 0x04 /* Turn on LED0 */
|
||
|
|
#define FPGA_REG0_LED1 0x02 /* Turn on LED1 */
|
||
|
|
#define FPGA_REG0_LED2 0x01 /* Turn on LED2 */
|
||
|
|
|
||
|
|
#define FPGA_REG1_SSPEC_DIS 0x80 /* C9531 Spread Spectrum disabled */
|
||
|
|
#define FPGA_REG1_OFFBD_PCICLK 0x40 /* Onboard PCI clock selected */
|
||
|
|
#define FPGA_REG1_CLOCK_MASK 0x30 /* Mask for C9531 output freq select */
|
||
|
|
#define FPGA_REG1_CLOCK_BIT_SHIFT 4
|
||
|
|
#define FPGA_REG1_PCI_INT_ARB 0x08 /* PCI Internal arbiter selected */
|
||
|
|
#define FPGA_REG1_PCI_FREQ 0x04 /* PCI Frequency select */
|
||
|
|
#define FPGA_REG1_OFFB_FLASH 0x02 /* Off board flash */
|
||
|
|
#define FPGA_REG1_SRAM_BOOT 0x01 /* SRAM at 0xFFF80000 not Flash */
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Internal Definitions
|
||
|
|
*
|
||
|
|
* Boot Flags
|
||
|
|
*/
|
||
|
|
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||
|
|
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||
|
|
|
||
|
|
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||
|
|
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||
|
|
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* __CONFIG_H */
|