350 lines
10 KiB
C
350 lines
10 KiB
C
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/*
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* (C) Copyright 2002
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
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#define CONFIG_HHP_CRADLE 1 /* on an Cradle Board */
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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/*
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* Size of malloc() pool
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*/
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#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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/*
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* Hardware drivers
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*/
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#define CONFIG_DRIVER_SMC91111
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#define CONFIG_SMC91111_BASE 0x10000300
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#define CONFIG_SMC91111_EXT_PHY
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#define CONFIG_SMC_USE_32_BIT
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/*
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* select serial console configuration
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*/
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#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL)
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_BOOTARGS "root=/dev/mtdblock2 console=ttyS0,115200"
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#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
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#define CONFIG_NETMASK 255.255.0.0
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#define CONFIG_IPADDR 192.168.0.21
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#define CONFIG_SERVERIP 192.168.0.250
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#define CONFIG_BOOTCOMMAND "bootm 40000"
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#define CONFIG_CMDLINE_TAG
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
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#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
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#define CFG_LOAD_ADDR 0xa2000000 /* default load address */
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#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
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#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
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/* valid baudrates */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE (128*1024) /* regular stack */
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
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#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
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#endif
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/*
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
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#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x01000000 /* 64 MB */
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#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
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#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
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#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
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#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
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#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
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#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
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#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
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#define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */
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#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
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#define CFG_DRAM_BASE 0xa0000000
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#define CFG_DRAM_SIZE 0x04000000
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#define CFG_FLASH_BASE PHYS_FLASH_1
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/*
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* FLASH and environment organization
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
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/* timeout values are in ticks */
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#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
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#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_ADDR 0x00020000 /* absolute address for now */
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#define CFG_ENV_SIZE 0x20000 /* 8K ouch, this may later be */
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/******************************************************************************
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*
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* CPU specific defines
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*
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******************************************************************************/
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/*
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* GPIO settings
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*
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* GPIO pin assignments
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* GPIO Name Dir Out AF
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* 0 NC
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* 1 NC
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* 2 SIRQ1 I
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* 3 SIRQ2 I
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* 4 SIRQ3 I
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* 5 DMAACK1 O 0
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* 6 DMAACK2 O 0
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* 7 DMAACK3 O 0
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* 8 TC1 O 0
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* 9 TC2 O 0
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* 10 TC3 O 0
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* 11 nDMAEN O 1
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* 12 AENCTRL O 0
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* 13 PLDTC O 0
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* 14 ETHIRQ I
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* 15 NC
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* 16 NC
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* 17 NC
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* 18 RDY I
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* 19 DMASIO I
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* 20 ETHIRQ NC
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* 21 NC
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* 22 PGMEN O 1 FIXME for debug only enable flash
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* 23 NC
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* 24 NC
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* 25 NC
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* 26 NC
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* 27 NC
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* 28 NC
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* 29 NC
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* 30 NC
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* 31 NC
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* 32 NC
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* 33 NC
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* 34 FFRXD I 01
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* 35 FFCTS I 01
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* 36 FFDCD I 01
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* 37 FFDSR I 01
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* 38 FFRI I 01
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* 39 FFTXD O 1 10
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* 40 FFDTR O 0 10
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* 41 FFRTS O 0 10
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* 42 RS232FOFF O 0 00
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* 43 NC
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* 44 NC
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* 45 IRSL0 O 0
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* 46 IRRX0 I 01
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* 47 IRTX0 O 0 10
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* 48 NC
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* 49 nIOWE O 0
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* 50 NC
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* 51 NC
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* 52 NC
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* 53 NC
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* 54 NC
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* 55 NC
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* 56 NC
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* 57 NC
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* 58 DKDIRQ I
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* 59 NC
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* 60 NC
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* 61 NC
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* 62 NC
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* 63 NC
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* 64 COMLED O 0
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* 65 COMLED O 0
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* 66 COMLED O 0
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* 67 COMLED O 0
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* 68 COMLED O 0
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* 69 COMLED O 0
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* 70 COMLED O 0
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* 71 COMLED O 0
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* 72 NC
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* 73 NC
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* 74 NC
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* 75 NC
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* 76 NC
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* 77 NC
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* 78 CSIO O 1
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* 79 NC
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* 80 CSETH O 1
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*
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* NOTE: All NC's are defined to be outputs
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*
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*/
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/* Pin direction control */
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/* NOTE GPIO 0, 61, 62 are set for inputs due to CPLD SPAREs */
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#define CFG_GPDR0_VAL 0xfff3bf02
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#define CFG_GPDR1_VAL 0xfbffbf83
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#define CFG_GPDR2_VAL 0x0001ffff
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/* Set and Clear registers */
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#define CFG_GPSR0_VAL 0x00400800
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#define CFG_GPSR1_VAL 0x00000480
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#define CFG_GPSR2_VAL 0x00014000
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#define CFG_GPCR0_VAL 0x00000000
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#define CFG_GPCR1_VAL 0x00000000
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#define CFG_GPCR2_VAL 0x00000000
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/* Edge detect registers (these are set by the kernel) */
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#define CFG_GRER0_VAL 0x00000000
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#define CFG_GRER1_VAL 0x00000000
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#define CFG_GRER2_VAL 0x00000000
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#define CFG_GFER0_VAL 0x00000000
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#define CFG_GFER1_VAL 0x00000000
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#define CFG_GFER2_VAL 0x00000000
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/* Alternate function registers */
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#define CFG_GAFR0_L_VAL 0x00000000
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#define CFG_GAFR0_U_VAL 0x00000010
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#define CFG_GAFR1_L_VAL 0x900a9550
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#define CFG_GAFR1_U_VAL 0x00000008
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#define CFG_GAFR2_L_VAL 0x20000000
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#define CFG_GAFR2_U_VAL 0x00000002
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/*
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* Clocks, power control and interrupts
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*/
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#define CFG_PSSR_VAL 0x00000020
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#define CFG_CCCR_VAL 0x00000141 /* 100 MHz memory, 200 MHz CPU */
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#define CFG_CKEN_VAL 0x00000060 /* FFUART and STUART enabled */
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#define CFG_ICMR_VAL 0x00000000 /* No interrupts enabled */
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/* FIXME
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*
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* RTC settings
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* Watchdog
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*
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*/
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/*
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* Memory settings
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*
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* FIXME Can ethernet be burst read and/or write?? This is set for lubbock
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* Verify timings on all
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*/
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#define CFG_MSC0_VAL 0x000023FA /* flash bank (cs0) */
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/*#define CFG_MSC1_VAL 0x00003549 / * SuperIO bank (cs2) */
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#define CFG_MSC1_VAL 0x0000354c /* SuperIO bank (cs2) */
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#define CFG_MSC2_VAL 0x00001224 /* Ethernet bank (cs4) */
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#ifdef REDBOOT_WAY
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#define CFG_MDCNFG_VAL 0x00001aa1 /* FIXME can DTC be 01? */
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#define CFG_MDMRS_VAL 0x00000000
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#define CFG_MDREFR_VAL 0x00018018
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#else
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#define CFG_MDCNFG_VAL 0x00001aa1 /* FIXME can DTC be 01? */
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#define CFG_MDMRS_VAL 0x00000000
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#define CFG_MDREFR_VAL 0x00403018 /* Initial setting, individual bits set in lowlevel_init.S */
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#endif
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/*
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* PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
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*/
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#define CFG_MECR_VAL 0x00000000
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#define CFG_MCMEM0_VAL 0x00010504
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#define CFG_MCMEM1_VAL 0x00010504
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#define CFG_MCATT0_VAL 0x00010504
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#define CFG_MCATT1_VAL 0x00010504
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#define CFG_MCIO0_VAL 0x00004715
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#define CFG_MCIO1_VAL 0x00004715
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/* Board specific defines */
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/* LED defines */
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#define YELLOW 0x03
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#define RED 0x02
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#define GREEN 0x01
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#define OFF 0x00
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#define LED_IRDA0 0
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#define LED_IRDA1 2
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#define LED_IRDA2 4
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#define LED_IRDA3 6
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#define CRADLE_LED_SET_REG GPSR2
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#define CRADLE_LED_CLR_REG GPCR2
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/* SuperIO defines */
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#define CRADLE_SIO_INDEX 0x2e
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#define CRADLE_SIO_DATA 0x2f
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/* IO defines */
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#define CRADLE_CPLD_PHYS 0x08000000
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#define CRADLE_SIO1_PHYS 0x08100000
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#define CRADLE_SIO2_PHYS 0x08200000
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#define CRADLE_SIO3_PHYS 0x08300000
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#define CRADLE_ETH_PHYS 0x10000000
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#ifndef __ASSEMBLY__
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/* global prototypes */
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void led_code(int code, int color);
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#endif
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#endif /* __CONFIG_H */
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