473 lines
15 KiB
C
473 lines
15 KiB
C
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/*
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* (C) Copyright 2000, 2001, 2002
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* Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
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*
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* Configuration for the Cogent CSB226 board. For details see
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* http://www.cogcomp.com/csb_csb226.htm
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* include/configs/csb226.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define DEBUG 1
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
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#define CONFIG_CSB226 1 /* on a CSB226 board */
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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/* for timer/console/ethernet */
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/*
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* Hardware drivers
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*/
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/*
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* select serial console configuration
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*/
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#define CONFIG_FFUART 1 /* we use FFUART on CSB226 */
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 19200
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#undef CONFIG_MISC_INIT_R /* not used yet */
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#define CONFIG_COMMANDS (CFG_CMD_BDI|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO|CFG_CMD_DHCP|CFG_CMD_CACHE)
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_BOOTARGS "console=ttyS0,19200 ip=192.168.1.10,192.168.1.5,,255,255,255,0,csb root=/dev/nfs, ether=0,0x08000000,eth0"
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#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_IPADDR 192.168.1.56
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#define CONFIG_SERVERIP 192.168.1.5
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#define CONFIG_BOOTCOMMAND "bootm 0x40000"
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#define CONFIG_SHOW_BOOT_PROGRESS
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#define CONFIG_CMDLINE_TAG 1
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*
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* Miscellaneous configurable options
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*/
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/*
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* Size of malloc() pool; this lives below the uppermost 128 KiB which are
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* used for the RAM copy of the uboot code
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*
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*/
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#define CFG_MALLOC_LEN (128*1024)
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "uboot> " /* Monitor Command Prompt */
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#define CFG_CBSIZE 128 /* Console I/O Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
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#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
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#define CFG_LOAD_ADDR 0xa3000000 /* default load address */
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/* RS: where is this documented? */
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/* RS: is this where U-Boot is */
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/* RS: relocated to in RAM? */
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#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
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/* RS: the oscillator is actually 3680130?? */
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#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
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/* 0101000001 */
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/* ^^^^^ Memory Speed 99.53 MHz */
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/* ^^ Run Mode Speed = 2x Mem Speed */
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/* ^^ Turbo Mode Sp. = 1x Run M. Sp. */
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#define CFG_MONITOR_LEN 0x20000 /* 128 KiB */
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/* valid baudrates */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Network chip
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*/
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#define CONFIG_DRIVER_CS8900 1
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#define CS8900_BUS32 1
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#define CS8900_BASE 0x08000000
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/*
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE (128*1024) /* regular stack */
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
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#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
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#endif
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/*
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
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#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
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#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
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#define CFG_DRAM_BASE 0xa0000000 /* RAM starts here */
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#define CFG_DRAM_SIZE 0x02000000
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#define CFG_FLASH_BASE PHYS_FLASH_1
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# if 0
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/* FIXME: switch to _documented_ registers */
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/*
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* GPIO settings
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*
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* GP15 == nCS1 is 1
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* GP24 == SFRM is 1
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* GP25 == TXD is 1
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* GP33 == nCS5 is 1
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* GP39 == FFTXD is 1
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* GP41 == RTS is 1
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* GP47 == TXD is 1
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* GP49 == nPWE is 1
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* GP62 == LED_B is 1
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* GP63 == TDM_OE is 1
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* GP78 == nCS2 is 1
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* GP79 == nCS3 is 1
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* GP80 == nCS4 is 1
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*/
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#define CFG_GPSR0_VAL 0x03008000
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#define CFG_GPSR1_VAL 0xC0028282
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#define CFG_GPSR2_VAL 0x0001C000
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/* GP02 == DON_RST is 0
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* GP23 == SCLK is 0
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* GP45 == USB_ACT is 0
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* GP60 == PLLEN is 0
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* GP61 == LED_A is 0
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* GP73 == SWUPD_LED is 0
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*/
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#define CFG_GPCR0_VAL 0x00800004
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#define CFG_GPCR1_VAL 0x30002000
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#define CFG_GPCR2_VAL 0x00000100
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/* GP00 == DON_READY is input
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* GP01 == DON_OK is input
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* GP02 == DON_RST is output
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* GP03 == RESET_IND is input
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* GP07 == RES11 is input
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* GP09 == RES12 is input
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* GP11 == SWUPDATE is input
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* GP14 == nPOWEROK is input
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* GP15 == nCS1 is output
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* GP17 == RES22 is input
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* GP18 == RDY is input
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* GP23 == SCLK is output
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* GP24 == SFRM is output
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* GP25 == TXD is output
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* GP26 == RXD is input
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* GP32 == RES21 is input
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* GP33 == nCS5 is output
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* GP34 == FFRXD is input
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* GP35 == CTS is input
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* GP39 == FFTXD is output
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* GP41 == RTS is output
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* GP42 == USB_OK is input
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* GP45 == USB_ACT is output
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* GP46 == RXD is input
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* GP47 == TXD is output
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* GP49 == nPWE is output
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* GP58 == nCPUBUSINT is input
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* GP59 == LANINT is input
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* GP60 == PLLEN is output
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* GP61 == LED_A is output
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* GP62 == LED_B is output
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* GP63 == TDM_OE is output
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* GP64 == nDSPINT is input
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* GP65 == STRAP0 is input
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* GP67 == STRAP1 is input
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* GP69 == STRAP2 is input
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* GP70 == STRAP3 is input
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* GP71 == STRAP4 is input
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* GP73 == SWUPD_LED is output
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* GP78 == nCS2 is output
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* GP79 == nCS3 is output
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* GP80 == nCS4 is output
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*/
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#define CFG_GPDR0_VAL 0x03808004
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#define CFG_GPDR1_VAL 0xF002A282
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#define CFG_GPDR2_VAL 0x0001C200
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/* GP15 == nCS1 is AF10
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* GP18 == RDY is AF01
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* GP23 == SCLK is AF10
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* GP24 == SFRM is AF10
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* GP25 == TXD is AF10
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* GP26 == RXD is AF01
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* GP33 == nCS5 is AF10
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* GP34 == FFRXD is AF01
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* GP35 == CTS is AF01
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* GP39 == FFTXD is AF10
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* GP41 == RTS is AF10
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* GP46 == RXD is AF10
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* GP47 == TXD is AF01
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* GP49 == nPWE is AF10
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* GP78 == nCS2 is AF10
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* GP79 == nCS3 is AF10
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* GP80 == nCS4 is AF10
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*/
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#define CFG_GAFR0_L_VAL 0x80000000
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#define CFG_GAFR0_U_VAL 0x001A8010
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#define CFG_GAFR1_L_VAL 0x60088058
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#define CFG_GAFR1_U_VAL 0x00000008
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#define CFG_GAFR2_L_VAL 0xA0000000
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#define CFG_GAFR2_U_VAL 0x00000002
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/* FIXME: set GPIO_RER/FER */
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/* RDH = 1
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* PH = 1
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* VFS = 1
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* BFS = 1
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* SSS = 1
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*/
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#define CFG_PSSR_VAL 0x37
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/*
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* Memory settings
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*
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* This is the configuration for nCS0/1 -> flash banks
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* configuration for nCS1:
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* [31] 0 - Slower Device
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* [30:28] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
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* [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
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* [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
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* [19] 1 - 16 Bit bus width
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* [18:16] 000 - nonburst RAM or FLASH
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* configuration for nCS0:
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* [15] 0 - Slower Device
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* [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
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* [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
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* [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
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* [03] 1 - 16 Bit bus width
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* [02:00] 000 - nonburst RAM or FLASH
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*/
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#define CFG_MSC0_VAL 0x25b825b8 /* flash banks */
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/* This is the configuration for nCS2/3 -> TDM-Switch, DSP
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* configuration for nCS3: DSP
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* [31] 0 - Slower Device
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* [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
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* [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
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* [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns
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* [19] 1 - 16 Bit bus width
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* [18:16] 100 - variable latency I/O
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* configuration for nCS2: TDM-Switch
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* [15] 0 - Slower Device
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* [14:12] 101 - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns
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* [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns
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* [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns
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* [03] 1 - 16 Bit bus width
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* [02:00] 100 - variable latency I/O
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*/
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#define CFG_MSC1_VAL 0x123C593C /* TDM switch, DSP */
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/* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
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*
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* configuration for nCS5: LAN Controller
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* [31] 0 - Slower Device
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* [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns
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* [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
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* [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
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* [19] 1 - 16 Bit bus width
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* [18:16] 100 - variable latency I/O
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* configuration for nCS4: ExtBus
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* [15] 0 - Slower Device
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* [14:12] 110 - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns
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* [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns
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* [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns
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* [03] 1 - 16 Bit bus width
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* [02:00] 100 - variable latency I/O
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*/
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#define CFG_MSC2_VAL 0x123C6CDC /* extra bus, LAN controller */
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/* MDCNFG: SDRAM Configuration Register
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*
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* [31:29] 000 - reserved
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* [28] 0 - no SA1111 compatiblity mode
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* [27] 0 - latch return data with return clock
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* [26] 0 - alternate addressing for pair 2/3
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* [25:24] 00 - timings
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* [23] 0 - internal banks in lower partition 2/3 (not used)
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* [22:21] 00 - row address bits for partition 2/3 (not used)
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* [20:19] 00 - column address bits for partition 2/3 (not used)
|
||
|
|
* [18] 0 - SDRAM partition 2/3 width is 32 bit
|
||
|
|
* [17] 0 - SDRAM partition 3 disabled
|
||
|
|
* [16] 0 - SDRAM partition 2 disabled
|
||
|
|
* [15:13] 000 - reserved
|
||
|
|
* [12] 1 - SA1111 compatiblity mode
|
||
|
|
* [11] 1 - latch return data with return clock
|
||
|
|
* [10] 0 - no alternate addressing for pair 0/1
|
||
|
|
* [09:08] 01 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
|
||
|
|
* [7] 1 - 4 internal banks in lower partition pair
|
||
|
|
* [06:05] 10 - 13 row address bits for partition 0/1
|
||
|
|
* [04:03] 01 - 9 column address bits for partition 0/1
|
||
|
|
* [02] 0 - SDRAM partition 0/1 width is 32 bit
|
||
|
|
* [01] 0 - disable SDRAM partition 1
|
||
|
|
* [00] 1 - enable SDRAM partition 0
|
||
|
|
*/
|
||
|
|
/* use the configuration above but disable partition 0 */
|
||
|
|
#define CFG_MDCNFG_VAL 0x000019c8
|
||
|
|
|
||
|
|
/* MDREFR: SDRAM Refresh Control Register
|
||
|
|
*
|
||
|
|
* [32:26] 0 - reserved
|
||
|
|
* [25] 0 - K2FREE: not free running
|
||
|
|
* [24] 0 - K1FREE: not free running
|
||
|
|
* [23] 1 - K0FREE: not free running
|
||
|
|
* [22] 0 - SLFRSH: self refresh disabled
|
||
|
|
* [21] 0 - reserved
|
||
|
|
* [20] 0 - APD: no auto power down
|
||
|
|
* [19] 0 - K2DB2: SDCLK2 is MemClk
|
||
|
|
* [18] 0 - K2RUN: disable SDCLK2
|
||
|
|
* [17] 0 - K1DB2: SDCLK1 is MemClk
|
||
|
|
* [16] 1 - K1RUN: enable SDCLK1
|
||
|
|
* [15] 1 - E1PIN: SDRAM clock enable
|
||
|
|
* [14] 1 - K0DB2: SDCLK0 is MemClk
|
||
|
|
* [13] 0 - K0RUN: disable SDCLK0
|
||
|
|
* [12] 1 - E0PIN: disable SDCKE0
|
||
|
|
* [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
|
||
|
|
*/
|
||
|
|
#define CFG_MDREFR_VAL 0x0081D018
|
||
|
|
|
||
|
|
/* MDMRS: Mode Register Set Configuration Register
|
||
|
|
*
|
||
|
|
* [31] 0 - reserved
|
||
|
|
* [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
|
||
|
|
* [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used)
|
||
|
|
* [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used)
|
||
|
|
* [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used)
|
||
|
|
* [15] 0 - reserved
|
||
|
|
* [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value.
|
||
|
|
* [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency.
|
||
|
|
* [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
|
||
|
|
* [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4.
|
||
|
|
*/
|
||
|
|
#define CFG_MDMRS_VAL 0x00020022
|
||
|
|
|
||
|
|
/*
|
||
|
|
* PCMCIA and CF Interfaces
|
||
|
|
*/
|
||
|
|
#define CFG_MECR_VAL 0x00000000
|
||
|
|
#define CFG_MCMEM0_VAL 0x00000000
|
||
|
|
#define CFG_MCMEM1_VAL 0x00000000
|
||
|
|
#define CFG_MCATT0_VAL 0x00000000
|
||
|
|
#define CFG_MCATT1_VAL 0x00000000
|
||
|
|
#define CFG_MCIO0_VAL 0x00000000
|
||
|
|
#define CFG_MCIO1_VAL 0x00000000
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/*
|
||
|
|
* GPIO settings
|
||
|
|
*/
|
||
|
|
#define CFG_GPSR0_VAL 0xFFFFFFFF
|
||
|
|
#define CFG_GPSR1_VAL 0xFFFFFFFF
|
||
|
|
#define CFG_GPSR2_VAL 0xFFFFFFFF
|
||
|
|
#define CFG_GPCR0_VAL 0x08022080
|
||
|
|
#define CFG_GPCR1_VAL 0x00000000
|
||
|
|
#define CFG_GPCR2_VAL 0x00000000
|
||
|
|
#define CFG_GPDR0_VAL 0xCD82A878
|
||
|
|
#define CFG_GPDR1_VAL 0xFCFFAB80
|
||
|
|
#define CFG_GPDR2_VAL 0x0001FFFF
|
||
|
|
#define CFG_GAFR0_L_VAL 0x80000000
|
||
|
|
#define CFG_GAFR0_U_VAL 0xA5254010
|
||
|
|
#define CFG_GAFR1_L_VAL 0x599A9550
|
||
|
|
#define CFG_GAFR1_U_VAL 0xAAA5AAAA
|
||
|
|
#define CFG_GAFR2_L_VAL 0xAAAAAAAA
|
||
|
|
#define CFG_GAFR2_U_VAL 0x00000002
|
||
|
|
|
||
|
|
/* FIXME: set GPIO_RER/FER */
|
||
|
|
|
||
|
|
#define CFG_PSSR_VAL 0x20
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Memory settings
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define CFG_MSC0_VAL 0x2ef15af0
|
||
|
|
#define CFG_MSC1_VAL 0x00003ff4
|
||
|
|
#define CFG_MSC2_VAL 0x7ff07ff0
|
||
|
|
#define CFG_MDCNFG_VAL 0x09a909a9
|
||
|
|
#define CFG_MDREFR_VAL 0x038ff030
|
||
|
|
#define CFG_MDMRS_VAL 0x00220022
|
||
|
|
|
||
|
|
/*
|
||
|
|
* PCMCIA and CF Interfaces
|
||
|
|
*/
|
||
|
|
#define CFG_MECR_VAL 0x00000000
|
||
|
|
#define CFG_MCMEM0_VAL 0x00000000
|
||
|
|
#define CFG_MCMEM1_VAL 0x00000000
|
||
|
|
#define CFG_MCATT0_VAL 0x00000000
|
||
|
|
#define CFG_MCATT1_VAL 0x00000000
|
||
|
|
#define CFG_MCIO0_VAL 0x00000000
|
||
|
|
#define CFG_MCIO1_VAL 0x00000000
|
||
|
|
|
||
|
|
#define CSB226_USER_LED0 0x00000008
|
||
|
|
#define CSB226_USER_LED1 0x00000010
|
||
|
|
#define CSB226_USER_LED2 0x00000020
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* FLASH and environment organization
|
||
|
|
*/
|
||
|
|
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||
|
|
#define CFG_MAX_FLASH_SECT 128 /* max number of sect. on one chip */
|
||
|
|
|
||
|
|
/* timeout values are in ticks */
|
||
|
|
#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
|
||
|
|
#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
|
||
|
|
|
||
|
|
#define CFG_ENV_IS_IN_FLASH 1
|
||
|
|
#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000)
|
||
|
|
/* Addr of Environment Sector */
|
||
|
|
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
|
||
|
|
|
||
|
|
#endif /* __CONFIG_H */
|