540 lines
18 KiB
C
540 lines
18 KiB
C
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/*
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* (C) Copyright 2001-2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* Workaround for layout bug on prototype board
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*/
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#define PCU_E_WITH_SWAPPED_CS 1
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC860 1 /* This is a MPC860T CPU */
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#define CONFIG_MPC860T 1
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#define CONFIG_PCU_E 1 /* ...on a PCU E board */
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#define CONFIG_BAUDRATE 9600
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#endif
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#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
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#undef CONFIG_BOOTARGS
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#define CONFIG_BOOTCOMMAND \
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"bootp;" \
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"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
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"bootm"
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_STATUS_LED 1 /* Status LED enabled */
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#define CONFIG_PRAM 2048 /* reserve 2 MB "protected RAM" */
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#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
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#define CONFIG_SPI /* enable SPI driver */
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#define CONFIG_SPI_X /* 16 bit EEPROM addressing */
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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/* ----------------------------------------------------------------
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* Offset to initial SPI buffers in DPRAM (used if the environment
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* is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to
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* use at an early stage. It is used between the two initialization
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* calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it
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* far enough from the start of the data area (as well as from the
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* stack pointer).
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* ---------------------------------------------------------------- */
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#define CFG_SPI_INIT_OFFSET 0xB00
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
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CFG_CMD_BSP | \
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CFG_CMD_DATE | \
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CFG_CMD_DHCP | \
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CFG_CMD_EEPROM | \
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CFG_CMD_NFS | \
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CFG_CMD_SNTP )
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#define CONFIG_BOOTP_MASK \
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((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY)
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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/*----------------------------------------------------------------------*/
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
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#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
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#define CFG_LOAD_ADDR 0x00100000 /* default load address */
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#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
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/* Ethernet hardware configuration done using port pins */
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#define CFG_PB_ETH_RESET 0x00000020 /* PB 26 */
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#if PCU_E_WITH_SWAPPED_CS /* XXX */
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#define CFG_PA_ETH_MDDIS 0x4000 /* PA 1 */
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#define CFG_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */
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#define CFG_PB_ETH_CFG1 0x00000400 /* PB 21 */
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#define CFG_PB_ETH_CFG2 0x00000200 /* PB 22 */
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#define CFG_PB_ETH_CFG3 0x00000100 /* PB 23 */
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#else /* XXX */
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#define CFG_PB_ETH_MDDIS 0x00000010 /* PB 27 */
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#define CFG_PB_ETH_POWERDOWN 0x00000100 /* PB 23 */
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#define CFG_PB_ETH_CFG1 0x00000200 /* PB 22 */
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#define CFG_PB_ETH_CFG2 0x00000400 /* PB 21 */
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#define CFG_PB_ETH_CFG3 0x00000800 /* PB 20 */
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#endif /* XXX */
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/* Ethernet settings:
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* MDIO enabled, autonegotiation, 10/100Mbps, half/full duplex
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*/
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#define CFG_ETH_MDDIS_VALUE 0
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#define CFG_ETH_CFG1_VALUE 1
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#define CFG_ETH_CFG2_VALUE 1
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#define CFG_ETH_CFG3_VALUE 1
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/* PUMA configuration */
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#if PCU_E_WITH_SWAPPED_CS /* XXX */
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#define CFG_PB_PUMA_PROG 0x00000010 /* PB 27 */
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#else /* XXX */
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#define CFG_PA_PUMA_PROG 0x4000 /* PA 1 */
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#endif /* XXX */
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#define CFG_PC_PUMA_DONE 0x0008 /* PC 12 */
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#define CFG_PC_PUMA_INIT 0x0004 /* PC 13 */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CFG_IMMR 0xFE000000
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Address accessed to reset the board - must not be mapped/assigned
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*/
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#define CFG_RESET_ADDRESS 0xFEFFFFFF
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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/* this is an ugly hack needed because of the silly non-constant address map */
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#define CFG_FLASH_BASE (0-flash_info[0].size-flash_info[1].size)
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#if defined(DEBUG)
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#else
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#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
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#endif
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 160 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
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#if 0
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/* Start port with environment in flash; switch to SPI EEPROM later */
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment */
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#define CFG_ENV_ADDR 0xFFFFE000 /* Address of Environment Sector */
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#define CFG_ENV_SECT_SIZE 0x2000 /* use the top-most 8k boot sector */
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#define CFG_ENV_IS_EMBEDDED 1 /* short-cut compile-time test */
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#else
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/* Final version: environment in EEPROM */
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#define CFG_ENV_IS_IN_EEPROM 1
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#define CFG_I2C_EEPROM_ADDR 0
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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#define CFG_ENV_OFFSET 1024
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#define CFG_ENV_SIZE 1024
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#endif
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#if defined(CONFIG_WATCHDOG)
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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#else
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
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#endif
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6
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*-----------------------------------------------------------------------
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* External Arbitration max. priority (7),
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* Debug pins configuration '11',
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* Asynchronous external master enable.
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*/
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/* => 0x70600200 */
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#define CFG_SIUMCR (SIUMCR_EARP7 | SIUMCR_DBGC11 | SIUMCR_AEME)
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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*/
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#define CFG_PISCR (PISCR_PS | PISCR_PITF)
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
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*-----------------------------------------------------------------------
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* Reset PLL lock status sticky bit, timer expired status bit and timer
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* interrupt status bit, set PLL multiplication factor !
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*/
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/* 0x00004080 */
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#define CFG_PLPRCR_MF 0 /* (0+1) * 50 = 50 MHz Clock */
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#define CFG_PLPRCR \
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( (CFG_PLPRCR_MF << PLPRCR_MF_SHIFT) | \
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PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
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/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
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PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \
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)
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#define CONFIG_8xx_GCLK_FREQ ((CFG_PLPRCR_MF+1)*50000000)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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*-----------------------------------------------------------------------
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* Set clock output, timebase and RTC source and divider,
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* power management and some other internal clocks
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*
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* Note: PITRTCLK is 50MHz / 512 = 97'656.25 Hz
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*/
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#define SCCR_MASK SCCR_EBDF11
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/* 0x01800000 */
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#define CFG_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \
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SCCR_RTDIV | SCCR_RTSEL | \
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/*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
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SCCR_EBDF00 | SCCR_DFSYNC00 | \
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SCCR_DFBRG00 | SCCR_DFNL000 | \
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SCCR_DFNH000 | SCCR_DFLCD100 | \
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SCCR_DFALCD01)
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/*-----------------------------------------------------------------------
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* RTCSC - Real-Time Clock Status and Control Register 11-27
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*-----------------------------------------------------------------------
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*
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* Note: RTC counts at PITRTCLK / 8'192 = 11.920928 Hz !!!
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*
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* Don't expect the "date" command to work without a 32kHz clock input!
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*/
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/* 0x00C3 => 0x0003 */
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#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
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/*-----------------------------------------------------------------------
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* RCCR - RISC Controller Configuration Register 19-4
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*-----------------------------------------------------------------------
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*/
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#define CFG_RCCR 0x0000
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/*-----------------------------------------------------------------------
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* RMDS - RISC Microcode Development Support Control Register
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*-----------------------------------------------------------------------
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*/
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#define CFG_RMDS 0
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/*-----------------------------------------------------------------------
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*
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* Interrupt Levels
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*-----------------------------------------------------------------------
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*/
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#define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
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/*-----------------------------------------------------------------------
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*
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*-----------------------------------------------------------------------
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*
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*/
|
||
|
|
#define CFG_DER 0
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Init Memory Controller:
|
||
|
|
*
|
||
|
|
* BR0/1 and OR0/1 (FLASH) - second Flash bank optional
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
|
||
|
|
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||
|
|
#define FLASH_BASE6_PRELIM 0xFF000000 /* FLASH bank #1 */
|
||
|
|
#else /* XXX */
|
||
|
|
#define FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank #1 */
|
||
|
|
#endif /* XXX */
|
||
|
|
|
||
|
|
/*
|
||
|
|
* used to re-map FLASH: restrict access enough but not too much to
|
||
|
|
* meddle with FLASH accesses
|
||
|
|
*/
|
||
|
|
#define CFG_REMAP_OR_AM 0xFF800000 /* OR addr mask */
|
||
|
|
#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
|
||
|
|
|
||
|
|
/* FLASH timing: CSNT = 0, ACS = 00, SCY = 8, EHTR = 1 */
|
||
|
|
#define CFG_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_EHTR)
|
||
|
|
|
||
|
|
#define CFG_OR0_REMAP ( CFG_REMAP_OR_AM | OR_ACS_DIV1 | OR_BI | \
|
||
|
|
CFG_OR_TIMING_FLASH)
|
||
|
|
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
|
||
|
|
CFG_OR_TIMING_FLASH)
|
||
|
|
/* 16 bit, bank valid */
|
||
|
|
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
|
||
|
|
|
||
|
|
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||
|
|
#define CFG_OR6_REMAP CFG_OR0_REMAP
|
||
|
|
#define CFG_OR6_PRELIM CFG_OR0_PRELIM
|
||
|
|
#define CFG_BR6_PRELIM ((FLASH_BASE6_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
|
||
|
|
#else /* XXX */
|
||
|
|
#define CFG_OR1_REMAP CFG_OR0_REMAP
|
||
|
|
#define CFG_OR1_PRELIM CFG_OR0_PRELIM
|
||
|
|
#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
|
||
|
|
#endif /* XXX */
|
||
|
|
|
||
|
|
/*
|
||
|
|
* BR2/OR2: SDRAM
|
||
|
|
*
|
||
|
|
* Multiplexed addresses, GPL5 output to GPL5_A (don't care)
|
||
|
|
*/
|
||
|
|
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||
|
|
#define SDRAM_BASE5_PRELIM 0x00000000 /* SDRAM bank */
|
||
|
|
#else /* XXX */
|
||
|
|
#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank */
|
||
|
|
#endif /* XXX */
|
||
|
|
#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map 128 MB (>SDRAM_MAX_SIZE!) */
|
||
|
|
#define SDRAM_TIMING OR_CSNT_SAM /* SDRAM-Timing */
|
||
|
|
|
||
|
|
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
|
||
|
|
|
||
|
|
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||
|
|
#define CFG_OR5_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
|
||
|
|
#define CFG_BR5_PRELIM ((SDRAM_BASE5_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
|
||
|
|
#else /* XXX */
|
||
|
|
#define CFG_OR2_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
|
||
|
|
#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
|
||
|
|
#endif /* XXX */
|
||
|
|
|
||
|
|
/*
|
||
|
|
* BR3/OR3: CAN Controller
|
||
|
|
* BR3: 0x10000401 OR3: 0xffff818a
|
||
|
|
*/
|
||
|
|
#define CAN_CTRLR_BASE 0x10000000 /* CAN Controller */
|
||
|
|
#define CAN_CTRLR_OR_AM 0xFFFF8000 /* 32 kB */
|
||
|
|
#define CAN_CTRLR_TIMING (OR_BI | OR_SCY_8_CLK | OR_SETA | OR_EHTR)
|
||
|
|
|
||
|
|
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||
|
|
#define CFG_BR4_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
|
||
|
|
#define CFG_OR4_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)
|
||
|
|
#else /* XXX */
|
||
|
|
#define CFG_BR3_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
|
||
|
|
#define CFG_OR3_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)
|
||
|
|
#endif /* XXX */
|
||
|
|
|
||
|
|
/*
|
||
|
|
* BR4/OR4: PUMA Config
|
||
|
|
*
|
||
|
|
* Memory controller will be used in 2 modes:
|
||
|
|
*
|
||
|
|
* - "read" mode:
|
||
|
|
* BR4: 0x10100801 OR4: 0xffff8530
|
||
|
|
* - "load" mode (chip select on UPM B):
|
||
|
|
* BR4: 0x101008c1 OR4: 0xffff8630
|
||
|
|
*
|
||
|
|
* Default initialization is in "read" mode
|
||
|
|
*/
|
||
|
|
#define PUMA_CONF_BASE 0x10100000 /* PUMA Config */
|
||
|
|
#define PUMA_CONF_OR_AM 0xFFFF8000 /* 32 kB */
|
||
|
|
#define PUMA_CONF_LOAD_TIMING (OR_ACS_DIV2 | OR_SCY_3_CLK)
|
||
|
|
#define PUMA_CONF_READ_TIMING (OR_G5LA | OR_BI | OR_SCY_3_CLK)
|
||
|
|
|
||
|
|
#define PUMA_CONF_BR_LOAD ((PUMA_CONF_BASE & BR_BA_MSK) | \
|
||
|
|
BR_PS_16 | BR_MS_UPMB | BR_V)
|
||
|
|
#define PUMA_CONF_OR_LOAD (PUMA_CONF_OR_AM | PUMA_CONF_LOAD_TIMING)
|
||
|
|
|
||
|
|
#define PUMA_CONF_BR_READ ((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
|
||
|
|
#define PUMA_CONF_OR_READ (PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING)
|
||
|
|
|
||
|
|
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||
|
|
#define CFG_BR3_PRELIM PUMA_CONF_BR_READ
|
||
|
|
#define CFG_OR3_PRELIM PUMA_CONF_OR_READ
|
||
|
|
#else /* XXX */
|
||
|
|
#define CFG_BR4_PRELIM PUMA_CONF_BR_READ
|
||
|
|
#define CFG_OR4_PRELIM PUMA_CONF_OR_READ
|
||
|
|
#endif /* XXX */
|
||
|
|
|
||
|
|
/*
|
||
|
|
* BR5/OR5: PUMA: SMA Bus 8 Bit
|
||
|
|
* BR5: 0x10200401 OR5: 0xffe0010a
|
||
|
|
*/
|
||
|
|
#define PUMA_SMA8_BASE 0x10200000 /* PUMA SMA Bus 8 Bit */
|
||
|
|
#define PUMA_SMA8_OR_AM 0xFFE00000 /* 2 MB */
|
||
|
|
#define PUMA_SMA8_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
|
||
|
|
|
||
|
|
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||
|
|
#define CFG_BR2_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
|
||
|
|
#define CFG_OR2_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
|
||
|
|
#else /* XXX */
|
||
|
|
#define CFG_BR5_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
|
||
|
|
#define CFG_OR5_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
|
||
|
|
#endif /* XXX */
|
||
|
|
|
||
|
|
/*
|
||
|
|
* BR6/OR6: PUMA: SMA Bus 16 Bit
|
||
|
|
* BR6: 0x10600801 OR6: 0xffe0010a
|
||
|
|
*/
|
||
|
|
#define PUMA_SMA16_BASE 0x10600000 /* PUMA SMA Bus 16 Bit */
|
||
|
|
#define PUMA_SMA16_OR_AM 0xFFE00000 /* 2 MB */
|
||
|
|
#define PUMA_SMA16_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
|
||
|
|
|
||
|
|
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||
|
|
#define CFG_BR1_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
|
||
|
|
#define CFG_OR1_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
|
||
|
|
#else /* XXX */
|
||
|
|
#define CFG_BR6_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
|
||
|
|
#define CFG_OR6_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
|
||
|
|
#endif /* XXX */
|
||
|
|
|
||
|
|
/*
|
||
|
|
* BR7/OR7: PUMA: external Flash
|
||
|
|
* BR7: 0x10a00801 OR7: 0xfe00010a
|
||
|
|
*/
|
||
|
|
#define PUMA_FLASH_BASE 0x10A00000 /* PUMA external Flash */
|
||
|
|
#define PUMA_FLASH_OR_AM 0xFE000000 /* 32 MB */
|
||
|
|
#define PUMA_FLASH_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
|
||
|
|
|
||
|
|
#define CFG_BR7_PRELIM ((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
|
||
|
|
#define CFG_OR7_PRELIM (PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA)
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Memory Periodic Timer Prescaler
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* periodic timer for refresh */
|
||
|
|
#define CFG_MPTPR 0x0200
|
||
|
|
|
||
|
|
/*
|
||
|
|
* MAMR settings for SDRAM
|
||
|
|
* 0x30104118 = Timer A period 0x30, MAMR_AMB_TYPE_1, MAMR_G0CLB_A10,
|
||
|
|
* MAMR_RLFB_1X, MAMR_WLFB_1X, MAMR_TLFB_8X
|
||
|
|
* 0x30904114 = - " - | Periodic Timer A Enable, MAMR_TLFB_4X
|
||
|
|
*/
|
||
|
|
/* periodic timer for refresh */
|
||
|
|
#define CFG_MAMR_PTA 0x30 /* = 48 */
|
||
|
|
|
||
|
|
#define CFG_MAMR ( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) | \
|
||
|
|
MAMR_AMA_TYPE_1 | \
|
||
|
|
MAMR_G0CLA_A10 | \
|
||
|
|
MAMR_RLFA_1X | \
|
||
|
|
MAMR_WLFA_1X | \
|
||
|
|
MAMR_TLFA_8X )
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Internal Definitions
|
||
|
|
*
|
||
|
|
* Boot Flags
|
||
|
|
*/
|
||
|
|
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||
|
|
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||
|
|
|
||
|
|
#endif /* __CONFIG_H */
|