278 lines
10 KiB
C
278 lines
10 KiB
C
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/*
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* (C) Copyright 2001
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_405GP 1 /* This is a PPC405 CPU */
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#define CONFIG_4xx 1 /* ...member of PPC4xx family */
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#define CONFIG_SBC405 1 /* ...on a WR SBC405 board */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
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#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
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#define CONFIG_BAUDRATE 9600
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#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot for the sbc405;echo;echo Type \"? or help\" to get on-line help;echo"
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#define CONFIG_RAMBOOT \
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"setenv bootargs root=/dev/ram rw nfsroot=${serverip}:${rootpath} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
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"bootm ffc00000 ffca0000"
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#define CONFIG_NFSBOOT \
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"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
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"bootm ffc00000"
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#undef CONFIG_BOOTARGS
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#define CONFIG_BOOTCOMMAND "version;echo;tftpboot ${loadaddr} ${loadfile};bootvx" /* autoboot command */
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 0 /* PHY address */
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#define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bootargs=emac(0,0)host:/T221ppc/target/config/sbc405/vxWorks.st " \
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"e=192.168.193.102:ffffffe0 h=192.168.193.100 u=target pw=hello " \
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"f=0x08 tn=sbc405 o=emac \0" \
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"env_startaddr=FF000000\0" \
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"env_endaddr=FF03FFFF\0" \
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"loadfile=vxWorks.st\0" \
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"loadaddr=0x01000000\0" \
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"net_load=tftpboot ${loadaddr} ${loadfile}\0" \
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"uboot_startaddr=FFFC0000\0" \
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"uboot_endaddr=FFFFFFFF\0" \
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"update=tftp ${loadaddr} u-boot.bin;" \
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"protect off ${uboot_startaddr} ${uboot_endaddr};" \
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"era ${uboot_startaddr} ${uboot_endaddr};" \
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"cp.b ${loadaddr} ${uboot_startaddr} ${filesize};" \
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"protect on ${uboot_startaddr} ${uboot_endaddr}\0" \
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"zapenv=protect off ${env_startaddr} ${env_endaddr};" \
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"era ${env_startaddr} ${env_endaddr};" \
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"protect on ${env_startaddr} ${env_endaddr}\0"
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
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CFG_CMD_BSP | \
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CFG_CMD_ELF | \
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CFG_CMD_I2C | \
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CFG_CMD_IRQ | \
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CFG_CMD_MII | \
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CFG_CMD_PCI | \
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CFG_CMD_PING | \
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CFG_CMD_SDRAM | \
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0 )
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
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#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */
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#define CONFIG_IPADDR 192.168.193.102
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#define CONFIG_NETMASK 255.255.255.224
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#define CONFIG_SERVERIP 192.168.193.119
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#define CONFIG_GATEWAYIP 192.168.193.97
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#undef CFG_HUSH_PARSER /* use "hush" command parser */
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#ifdef CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#endif
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
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#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
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#define CFG_BASE_BAUD 691200
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/* The following table includes the supported baudrates */
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#define CFG_BAUDRATE_TABLE \
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{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
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57600, 115200, 230400, 460800, 921600 }
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_EXTBDINFO 1 /* To use extended board_info (bd_t) */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
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#define PCI_HOST_FORCE 1 /* configure as pci host */
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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/* resource configuration */
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#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
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#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
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#define CFG_PCI_SUBSYS_DEVICEID 0x0408 /* PCI Device ID: PMC-405 */
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#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
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#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
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#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
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#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
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#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
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#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
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#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_MONITOR_BASE 0xFFFC0000
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
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#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_FLASH_BASE 0xFF000000
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#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */
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#define CFG_FLASH_INCREMENT 0x01000000
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#undef CFG_FLASH_PROTECTION /* don't use hardware protection */
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#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
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/*-----------------------------------------------------------------------
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* Environment Variable setup
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*/
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#define CFG_ENV_ADDR CFG_FLASH_BASE /* starting right at the beginning */
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_OFFSET 0 /* starting right at the beginning */
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#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
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#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
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/* have only 8kB, 16kB is save here */
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#define CFG_CACHELINE_SIZE 32 /* ... */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* External Bus Controller (EBC) Setup
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*/
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#define FLASH0_BA CFG_FLASH_BASE /* FLASH 0 Base Address */
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/* Memory Bank 0 (Flash Bank 0) initialization */
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#define CFG_EBC_PB0AP 0x92015480
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#define CFG_EBC_PB0CR FLASH0_BA | 0x9C000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=32bit*/
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in data cache)
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*/
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/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
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#define CFG_TEMP_STACK_OCM 1
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/* On Chip Memory location */
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#define CFG_OCM_DATA_ADDR 0xF8000000
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#define CFG_OCM_DATA_SIZE 0x1000
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#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
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#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Definitions for Serial Presence Detect EEPROM address
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* (to get SDRAM settings)
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*/
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#define SPD_EEPROM_ADDRESS 0x50
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#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#endif /* __CONFIG_H */
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