214 lines
9.3 KiB
C
214 lines
9.3 KiB
C
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/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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This software file (the "File") is owned and distributed by Marvell
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International Ltd. and/or its affiliates ("Marvell") under the following
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alternative licensing terms. Once you have made an election to distribute the
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File under one of the following license alternatives, please (i) delete this
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introductory statement regarding license alternatives, (ii) delete the two
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license alternatives that you have not elected to use and (iii) preserve the
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Marvell copyright notice above.
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********************************************************************************
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Marvell Commercial License Option
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If you received this File from Marvell and you have entered into a commercial
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license agreement (a "Commercial License") with Marvell, the File is licensed
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to you under the terms of the applicable Commercial License.
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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********************************************************************************
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Marvell BSD License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File under the following licensing terms.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Marvell nor the names of its contributors may be
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used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#ifndef __INCnBootstraph
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#define __INCnBootstraph
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/* includes */
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/* defines */
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#define _DDR2
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#define SDRAM_CONFIG_REG_DV 0x03154400 /* 1400 */
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#define SDRAM_DUNIT_CTRL_REG_DV 0x04041040 /* 1404 */
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#define SDRAM_TIMING_CTRL_LOW_REG_DVAL 0x11712220 /* 1408 */
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#define SDRAM_TIMING_CTRL_HIGH_REG_DVAL 0x00000104 /* 140C */
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#define SDRAM_ADDR_CTRL_REG_DV 0x00000020 /* 1410 */
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#define SDRAM_OPEN_PAGE_CTRL_REG_DV 0x00000000 /* 1414 */
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#define SDRAM_MODE_REG_DV 0x00000432 /* 141C */
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#define SDRAM_EXTENDED_MODE_REG_DV 0x00000440 /* 1420 */
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#define SDRAM_FTDLL_CONFIG_REG_DV 0x00f95000 /* 1484 */
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#define DDR2_SDRAM_ODT_CTRL_LOW_REG_DV 0x84210000 /* 1494 */
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#define DDR2_SDRAM_ODT_CTRL_HIGH_REG_DV 0x00000000 /* 1498 */
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#define DDR2_DUNIT_ODT_CTRL_REG_DV 0x0000780f /* 149C */
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#define SDRAM_SIZE_REG_DV 0x07ff0001 /* 128MB */
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/* NAND Flash access */
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#define NAND_CMD_PORT (0x1 << (NFLASH_DEV_WIDTH >> 4))
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#define NAND_ADDR_PORT (0x2 << (NFLASH_DEV_WIDTH >> 4))
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/* NAND Flash Chip Capability */
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#ifdef MV_LARGE_PAGE
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#define NUM_BLOCKS 2048
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#define PAGES_PER_BLOCK 64
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#define PAGE_SIZE 2048 /* Bytes */
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#define SPARE_SIZE 64
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#define CFG_NAND_PAGE_SIZE (2048) /* NAND chip page size */
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#define CFG_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */
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#define CFG_NAND_PAGE_COUNT (64) /* NAND chip page count */
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#define CFG_NAND_BAD_BLOCK_POS (0) /* Location of bad block marker */
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#define CFG_NAND_U_BOOT_OFFS CFG_MONITOR_BASE /* Offset to U-Boot image */
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#define CFG_NAND_U_BOOT_SIZE CFG_MONITOR_LEN /* Size of RAM U-Boot image */
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#define CFG_NAND_U_BOOT_DST CFG_MONITOR_IMAGE_DST /* Load NUB to this addr */
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#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
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#else /* ! LARGE PAGE NAND */
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/* NAND Flash Chip Capability */
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#define NUM_BLOCKS 2048
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#define PAGES_PER_BLOCK 32
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#define PAGE_SIZE 512 /* Bytes */
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#define SPARE_SIZE 16
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#define CFG_NAND_PAGE_SIZE (512) /* NAND chip page size */
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#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
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#define CFG_NAND_PAGE_COUNT (32) /* NAND chip page count */
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#define CFG_NAND_BAD_BLOCK_POS (5) /* Location of bad block marker */
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#define CFG_NAND_U_BOOT_OFFS CFG_MONITOR_BASE /* Offset to U-Boot image */
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#define CFG_NAND_U_BOOT_SIZE CFG_MONITOR_LEN /* Size of RAM U-Boot image */
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#define CFG_NAND_U_BOOT_DST CFG_MONITOR_IMAGE_DST /* Load NUB to this addr */
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#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
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#endif
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/* NAND Flash Command. This appears to be generic across all NAND flash chips */
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#define CMD_READ 0x00 /* Read */
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#define CMD_READ1 0x01 /* Read1 */
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#define CMD_READ2 0x50 /* Read2 */
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#define CMD_START_READ 0x30 /* Read command after write addr */
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#define CMD_READID 0x90 /* ReadID */
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#define CMD_READID2 0x91 /* Read extended ID */
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#define CMD_WRITE 0x80 /* Write phase 1 */
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#define CMD_WRITE2 0x10 /* Write phase 2 */
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#define CMD_ERASE 0x60 /* Erase phase 1 */
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#define CMD_ERASE2 0xd0 /* Erase phase 2 */
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#define CMD_STATUS 0x70 /* Status read */
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#define CMD_RESET 0xff /* Reset */
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/* Status bit pattern */
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#define STATUS_READY 0x40 /* Ready */
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#define STATUS_ERROR 0x01 /* Error */
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#define NFLASH_DEV_WIDTH 8
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#ifdef MV_LARGE_PAGE
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#define BOOTER_PAGE_NUM 2
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#define BOOTER_BASE 0x00020000 + PAGE_SIZE
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#else
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#define BOOTER_PAGE_NUM 5
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#define BOOTER_BASE 0x00020000 + (3 * PAGE_SIZE)
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#endif /* MV_LARGE_PAGE */
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#define BOOTER_END (BOOTER_BASE + (BOOTER_PAGE_NUM * PAGE_SIZE))
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#undef INTER_REGS_BASE
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#define INTER_REGS_BASE 0xd0000000
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#if defined(MV_BOOTROM)
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#if defined(MV_88F6082)
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#define NAND_FLASH_BASE 0xD8000000
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#endif
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#if defined(MV_88F5182)
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#define NAND_FLASH_BASE 0xf0000000
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#endif
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#else
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#define NAND_FLASH_BASE 0xffff0000
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#endif /* defined(MV_BOOTROM) */
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#if 0
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#define NBOOT_UART_CHAN 0
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#define NBOOT_BAUDRATE 115200
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#define NBOOT_TIMER_NUM 0
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/* CPU config register (0x20100) bit[15:8] value for CPU to DDR clock ratio */
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#define CPU_2_MBUSL_DDR_CLK 0x0000 /* clock ratio 1x2 */
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/* #define CPU_2_MBUSL_DDR_CLK 0x2100 *//* clock ratio 1x3 */
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/* #define CPU_2_MBUSL_DDR_CLK 0x2200 *//* clock ratio 1x4 */
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/* Load General Purpose Register (GPR) with 32-bit constant value */
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#define GPR_LOAD(reg, val) \
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mov reg, $(val & 0xFF) ;\
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orr reg, reg, $(val & 0xFF00) ;\
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orr reg, reg, $(val & 0xFF0000) ;\
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orr reg, reg, $(val & 0xFF000000)
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/* Register Read/Write */
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#define MV_REG_READ_ASM(toReg, baseReg, regOffs) \
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ldr toReg, [baseReg, $(regOffs & 0xFFF)]
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#define MV_REG_WRITE_ASM(fromReg, baseReg, regOffs) \
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str fromReg, [baseReg, $(regOffs & 0xFFF)]
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/* 32bit byte swap. For example 0x11223344 -> 0x44332211 */
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#define MV_BYTE_SWAP_32BIT(X) ((((X)&0xff)<<24) | \
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(((X)&0xff00)<<8) | \
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(((X)&0xff0000)>>8) | \
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(((X)&0xff000000)>>24))
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/* Endianess macros. */
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#if defined(MV_CPU_LE)
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#define MV_32BIT_LE(X) (X)
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#define MV_32BIT_BE(X) MV_BYTE_SWAP_32BIT(X)
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#elif defined(MV_CPU_BE)
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#define MV_32BIT_LE(X) MV_BYTE_SWAP_32BIT(X)
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#define MV_32BIT_BE(X) (X)
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#else
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#error "CPU endianess isn't defined!\n"
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#endif
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#endif
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#endif /* __INCnBootstraph */
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