281 lines
8.0 KiB
ArmAsm
281 lines
8.0 KiB
ArmAsm
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/*
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* Board specific setup info
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*
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* (C) Copyright 2004 Ales Jindra <jindra@2n.cz>
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* (C) Copyright 2005 Ladislav Michl <michl@2n.cz>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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_TEXT_BASE:
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.word TEXT_BASE /* SDRAM load addr from config.mk */
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OMAP5910_LPG1_BASE: .word 0xfffbd000
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OMAP5910_TIPB_SWITCHES_BASE: .word 0xfffbc800
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OMAP5910_MPU_TC_BASE: .word 0xfffecc00
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OMAP5910_MPU_CLKM_BASE: .word 0xfffece00
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OMAP5910_ULPD_PWR_MNG_BASE: .word 0xfffe0800
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OMAP5910_DPLL1_BASE: .word 0xfffecf00
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OMAP5910_GPIO_BASE: .word 0xfffce000
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OMAP5910_MPU_WD_TIMER_BASE: .word 0xfffec800
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OMAP5910_MPUI_BASE: .word 0xfffec900
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_OMAP5910_ARM_CKCTL: .word OMAP5910_ARM_CKCTL
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_OMAP5910_ARM_EN_CLK: .word OMAP5910_ARM_EN_CLK
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OMAP5910_MPUI_CTRL: .word 0x0000ff1b
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VAL_EMIFS_CS0_CONFIG: .word 0x00009090
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VAL_EMIFS_CS1_CONFIG: .word 0x00003031
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VAL_EMIFS_CS2_CONFIG: .word 0x00003031
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VAL_EMIFS_CS3_CONFIG: .word 0x0000c0c0
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VAL_EMIFS_DYN_WAIT: .word 0x00000000
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/* autorefresh counter 0x246 ((64000000/13.4)-400)/8192) */
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/* SLRF SD_RET ARE SDRAM_TYPE ARCV SDRAM_FREQUENCY PWD CLK */
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VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27))
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VAL_EMIFF_SDRAM_CONFIG2: .word 0x00000003
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VAL_EMIFF_MRS: .word 0x00000037
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/*
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* GPIO04 - D4 (Onboard LED)
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* GPIO07 - LAN91C111 reset
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*/
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GPIO_DIRECTION:
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.word 0x0000ff6f
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/*
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* Disable everything, but D4 LED (connected through invertor)
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*/
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GPIO_OUTPUT:
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.word 0x00000010
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MUX_CONFIG_BASE:
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.word 0xfffe1000
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MUX_CONFIG_VALUES:
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.align 4
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.word 0x00000000 @ FUNC_MUX_CTRL_0
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.word 0x00000000 @ FUNC_MUX_CTRL_1
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.word 0x00000000 @ FUNC_MUX_CTRL_2
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.word 0x00000000 @ FUNC_MUX_CTRL_3
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.word 0x00000000 @ FUNC_MUX_CTRL_4
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.word 0x12082480 @ FUNC_MUX_CTRL_5
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.word 0x00000004 @ FUNC_MUX_CTRL_6
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.word 0x00000003 @ FUNC_MUX_CTRL_7
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.word 0x10001200 @ FUNC_MUX_CTRL_8
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.word 0x01201012 @ FUNC_MUX_CTRL_9
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.word 0x02081248 @ FUNC_MUX_CTRL_A
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.word 0x00001248 @ FUNC_MUX_CTRL_B
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.word 0x12240000 @ FUNC_MUX_CTRL_C
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.word 0x00002000 @ FUNC_MUX_CTRL_D
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.word 0x00000000 @ PULL_DWN_CTRL_0
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.word 0x0000085f @ PULL_DWN_CTRL_1
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.word 0x01001000 @ PULL_DWN_CTRL_2
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.word 0x00000000 @ PULL_DWN_CTRL_3
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.word 0x00000000 @ GATE_INH_CTRL_0
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.word 0x00000000 @ VOLTAGE_CTRL_0
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.word 0x00000000 @ TEST_DBG_CTRL_0
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.word 0x00000006 @ MOD_CONF_CTRL_0
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.word 0x0000eaef @ COMP_MODE_CTRL_0
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MUX_CONFIG_OFFSETS:
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.align 1
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.byte 0x00 @ FUNC_MUX_CTRL_0
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.byte 0x04 @ FUNC_MUX_CTRL_1
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.byte 0x08 @ FUNC_MUX_CTRL_2
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.byte 0x10 @ FUNC_MUX_CTRL_3
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.byte 0x14 @ FUNC_MUX_CTRL_4
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.byte 0x18 @ FUNC_MUX_CTRL_5
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.byte 0x1c @ FUNC_MUX_CTRL_6
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.byte 0x20 @ FUNC_MUX_CTRL_7
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.byte 0x24 @ FUNC_MUX_CTRL_8
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.byte 0x28 @ FUNC_MUX_CTRL_9
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.byte 0x2c @ FUNC_MUX_CTRL_A
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.byte 0x30 @ FUNC_MUX_CTRL_B
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.byte 0x34 @ FUNC_MUX_CTRL_C
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.byte 0x38 @ FUNC_MUX_CTRL_D
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.byte 0x40 @ PULL_DWN_CTRL_0
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.byte 0x44 @ PULL_DWN_CTRL_1
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.byte 0x48 @ PULL_DWN_CTRL_2
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.byte 0x4c @ PULL_DWN_CTRL_3
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.byte 0x50 @ GATE_INH_CTRL_0
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.byte 0x60 @ VOLTAGE_CTRL_0
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.byte 0x70 @ TEST_DBG_CTRL_0
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.byte 0x80 @ MOD_CONF_CTRL_0
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.byte 0x0c @ COMP_MODE_CTRL_0
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.byte 0xff
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.globl lowlevel_init
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lowlevel_init:
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/* Improve performance a bit... */
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mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register
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mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register
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mrc p15, 0, r1, c1, c0, 0 @ read C15 Control register
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orr r1, r1, #0x1000 @ enable I-cache, map interrupt vector 0xffff0000
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mcr p15, 0, r1, c1, c0, 0 @ write C15 Control register
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mov r1, #0x00
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mcr p15, 0, r1, c7, c5, 0 @ Flush I-cache
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nop
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nop
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nop
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nop
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/* Setup clocking mode */
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ldr r0, OMAP5910_MPU_CLKM_BASE @ prepare base of CLOCK unit
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ldrh r1, [r0, #0x18] @ get reset status
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bic r1, r1, #(7 << 11) @ clear clock select
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orr r1, r1, #(2 << 11) @ set synchronous scalable
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mov r2, #0 @ set wait counter to 100 clock cycles
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icache_loop:
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cmp r2, #0x01
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streqh r1, [r0, #0x18]
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add r2, r2, #0x01
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cmp r2, #0x10
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bne icache_loop
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nop
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/* Setup clock divisors */
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ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
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ldr r1, _OMAP5910_ARM_CKCTL
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orr r1, r1, #0x2000 @ enable DSP clock
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strh r1, [r0, #0x00] @ setup clock divisors
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/* Setup DPLL to generate requested freq */
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ldr r0, OMAP5910_DPLL1_BASE @ base of DPLL1 register
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mov r1, #0x0010 @ set PLL_ENABLE
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orr r1, r1, #0x2000 @ set IOB to new locking
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orr r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF
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orr r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF
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strh r1, [r0] @ write
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locking:
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ldrh r1, [r0] @ get DPLL value
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tst r1, #0x01
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beq locking @ while LOCK not set
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/* Enable clock */
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ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
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mov r1, #(1 << 10) @ disable idle mode do not check
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@ nWAKEUP pin, other remain active
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strh r1, [r0, #0x04]
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ldr r1, _OMAP5910_ARM_EN_CLK
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strh r1, [r0, #0x08]
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mov r1, #0x003f @ FLASH.RP not enabled in idle and
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@ max delayed ( 32 x CLKIN )
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strh r1, [r0, #0x0c]
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/* Configure 5910 pins functions to match our board. */
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ldr r0, MUX_CONFIG_BASE
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adr r1, MUX_CONFIG_VALUES
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adr r2, MUX_CONFIG_OFFSETS
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next_mux_cfg:
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ldrb r3, [r2], #1
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ldr r4, [r1], #4
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cmp r3, #0xff
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strne r4, [r0, r3]
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bne next_mux_cfg
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/* Configure GPIO pins (also enables onboard LED) */
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ldr r0, OMAP5910_GPIO_BASE
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ldr r1, GPIO_OUTPUT
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strh r1, [r0, #0x04]
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ldr r1, GPIO_DIRECTION
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strh r1, [r0, #0x08]
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/* EnablePeripherals */
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ldr r0, OMAP5910_MPU_CLKM_BASE @ CLOCK unit
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mov r1, #0x0001 @ Peripheral enable
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strh r1, [r0, #0x14]
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/* Program LED Pulse Generator */
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ldr r0, OMAP5910_LPG1_BASE @ 1st LED Pulse Generator
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mov r1, #0x7F @ Set obscure frequency in
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strb r1, [r0, #0x00] @ LCR
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mov r1, #0x01 @ Enable clock (CLK_EN) in
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strb r1, [r0, #0x04] @ PMR
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/* TIPB Lock UART1 */
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ldr r0, OMAP5910_TIPB_SWITCHES_BASE @ prepare base of TIPB switches
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mov r1, #1 @ ARM allocated
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strh r1, [r0,#0x04] @ clear IRQ line and status bits
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strh r1, [r0,#0x00]
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ldrh r1, [r0,#0x04]
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/* Disable watchdog */
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ldr r0, OMAP5910_MPU_WD_TIMER_BASE
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mov r1, #0xf5
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strh r1, [r0, #0x8]
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mov r1, #0xa0
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strh r1, [r0, #0x8]
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/* Enable MCLK */
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ldr r0, OMAP5910_ULPD_PWR_MNG_BASE
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mov r1, #0x6
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strh r1, [r0, #0x34]
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strh r1, [r0, #0x34]
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/* Setup clock divisors */
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ldr r0, OMAP5910_ULPD_PWR_MNG_BASE @ base of ULDPL DPLL1 register
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mov r1, #0x0010 @ set PLL_ENABLE
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orr r1, r1, #0x2000 @ set IOB to new locking
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strh r1, [r0] @ write
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ulocking:
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ldrh r1, [r0] @ get DPLL value
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tst r1, #1
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beq ulocking @ while LOCK not set
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/* EMIF init */
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ldr r0, OMAP5910_MPU_TC_BASE
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ldrh r1, [r0, #0x0c] @ EMIFS_CONFIG_REG
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bic r1, r1, #0x0c @ pwr down disabled, flash WP
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orr r1, r1, #0x01
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str r1, [r0, #0x0c]
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ldr r1, VAL_EMIFS_CS0_CONFIG
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str r1, [r0, #0x10] @ EMIFS_CS0_CONFIG
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ldr r1, VAL_EMIFS_CS1_CONFIG
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str r1, [r0, #0x14] @ EMIFS_CS1_CONFIG
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ldr r1, VAL_EMIFS_CS2_CONFIG
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str r1, [r0, #0x18] @ EMIFS_CS2_CONFIG
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ldr r1, VAL_EMIFS_CS3_CONFIG
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str r1, [r0, #0x1c] @ EMIFS_CS3_CONFIG
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ldr r1, VAL_EMIFS_DYN_WAIT
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str r1, [r0, #0x40] @ EMIFS_CFG_DYN_WAIT
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/* Setup SDRAM */
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ldr r1, VAL_EMIFF_SDRAM_CONFIG
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str r1, [r0, #0x20] @ EMIFF_SDRAM_CONFIG
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ldr r1, VAL_EMIFF_SDRAM_CONFIG2
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str r1, [r0, #0x3c] @ EMIFF_SDRAM_CONFIG2
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ldr r1, VAL_EMIFF_MRS
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str r1, [r0, #0x24] @ EMIFF_MRS
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/* SDRAM needs 100us to stabilize */
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mov r0, #0x4000
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sdelay:
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subs r0, r0, #0x1
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bne sdelay
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/* back to arch calling code */
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mov pc, lr
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.end
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