292 lines
13 KiB
C
292 lines
13 KiB
C
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/******************************************************************************
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*
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* Author: Xilinx, Inc.
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
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* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
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* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
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* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
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* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
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* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
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* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
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* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
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* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
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* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
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* FITNESS FOR A PARTICULAR PURPOSE.
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*
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*
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* Xilinx hardware products are not intended for use in life support
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* appliances, devices, or systems. Use in such applications is
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* expressly prohibited.
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*
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*
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* (c) Copyright 2002-2004 Xilinx Inc.
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* All rights reserved.
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*
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* FILENAME:
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*
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* xdma_channel.h
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*
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* DESCRIPTION:
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*
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* This file contains the DMA channel component implementation. This component
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* supports a distributed DMA design in which each device can have it's own
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* dedicated DMA channel, as opposed to a centralized DMA design.
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* A device which uses DMA typically contains two DMA channels, one for
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* sending data and the other for receiving data.
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*
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* This component is designed to be used as a basic building block for
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* designing a device driver. It provides registers accesses such that all
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* DMA processing can be maintained easier, but the device driver designer
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* must still understand all the details of the DMA channel.
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*
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* The DMA channel allows a CPU to minimize the CPU interaction required to move
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* data between a memory and a device. The CPU requests the DMA channel to
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* perform a DMA operation and typically continues performing other processing
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* until the DMA operation completes. DMA could be considered a primitive form
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* of multiprocessing such that caching and address translation can be an issue.
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*
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* Scatter Gather Operations
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*
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* The DMA channel may support scatter gather operations. A scatter gather
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* operation automates the DMA channel such that multiple buffers can be
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* sent or received with minimal software interaction with the hardware. Buffer
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* descriptors, contained in the XBufDescriptor component, are used by the
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* scatter gather operations of the DMA channel to describe the buffers to be
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* processed.
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*
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* Scatter Gather List Operations
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*
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* A scatter gather list may be supported by each DMA channel. The scatter
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* gather list allows buffer descriptors to be put into the list by a device
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* driver which requires scatter gather. The hardware processes the buffer
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* descriptors which are contained in the list and modifies the buffer
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* descriptors to reflect the status of the DMA operations. The device driver
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* is notified by interrupt that specific DMA events occur including scatter
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* gather events. The device driver removes the completed buffer descriptors
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* from the scatter gather list to evaluate the status of each DMA operation.
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*
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* The scatter gather list is created and buffer descriptors are inserted into
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* the list. Buffer descriptors are never removed from the list after it's
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* creation such that a put operation copies from a temporary buffer descriptor
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* to a buffer descriptor in the list. Get operations don't copy from the list
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* to a temporary, but return a pointer to the buffer descriptor in the list.
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* A buffer descriptor in the list may be locked to prevent it from being
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* overwritten by a put operation. This allows the device driver to get a
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* descriptor from a scatter gather list and prevent it from being overwritten
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* until the buffer associated with the buffer descriptor has been processed.
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*
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* Typical Scatter Gather Processing
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*
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* The following steps illustrate the typical processing to use the
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* scatter gather features of a DMA channel.
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*
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* 1. Create a scatter gather list for the DMA channel which puts empty buffer
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* descriptors into the list.
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* 2. Create buffer descriptors which describe the buffers to be filled with
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* receive data or the buffers which contain data to be sent.
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* 3. Put buffer descriptors into the DMA channel scatter list such that scatter
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* gather operations are requested.
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* 4. Commit the buffer descriptors in the list such that they are ready to be
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* used by the DMA channel hardware.
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* 5. Start the scatter gather operations of the DMA channel.
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* 6. Process any interrupts which occur as a result of the scatter gather
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* operations or poll the DMA channel to determine the status.
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*
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* Interrupts
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*
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* Each DMA channel has the ability to generate an interrupt. This component
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* does not perform processing for the interrupt as this processing is typically
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* tightly coupled with the device which is using the DMA channel. It is the
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* responsibility of the caller of DMA functions to manage the interrupt
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* including connecting to the interrupt and enabling/disabling the interrupt.
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*
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* Critical Sections
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*
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* It is the responsibility of the device driver designer to use critical
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* sections as necessary when calling functions of the DMA channel. This
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* component does not use critical sections and it does access registers using
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* read-modify-write operations. Calls to DMA functions from a main thread
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* and from an interrupt context could produce unpredictable behavior such that
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* the caller must provide the appropriate critical sections.
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*
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* Address Translation
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*
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* All addresses of data structures which are passed to DMA functions must
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* be physical (real) addresses as opposed to logical (virtual) addresses.
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*
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* Caching
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*
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* The memory which is passed to the function which creates the scatter gather
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* list must not be cached such that buffer descriptors are non-cached. This
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* is necessary because the buffer descriptors are kept in a ring buffer and
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* not directly accessible to the caller of DMA functions.
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*
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* The caller of DMA functions is responsible for ensuring that any data
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* buffers which are passed to the DMA channel are cache-line aligned if
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* necessary.
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*
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* The caller of DMA functions is responsible for ensuring that any data
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* buffers which are passed to the DMA channel have been flushed from the cache.
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*
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* The caller of DMA functions is responsible for ensuring that the cache is
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* invalidated prior to using any data buffers which are the result of a DMA
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* operation.
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*
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* Memory Alignment
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*
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* The addresses of data buffers which are passed to DMA functions must be
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* 32 bit word aligned since the DMA hardware performs 32 bit word transfers.
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*
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* Mutual Exclusion
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*
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* The functions of the DMA channel are not thread safe such that the caller
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* of all DMA functions is responsible for ensuring mutual exclusion for a
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* DMA channel. Mutual exclusion across multiple DMA channels is not
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* necessary.
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*
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* NOTES:
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*
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* Many of the provided functions which are register accessors don't provide
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* a lot of error detection. The caller is expected to understand the impact
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* of a function call based upon the current state of the DMA channel. This
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* is done to minimize the overhead in this component.
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*
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******************************************************************************/
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#ifndef XDMA_CHANNEL_H /* prevent circular inclusions */
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#define XDMA_CHANNEL_H /* by using protection macros */
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/***************************** Include Files *********************************/
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#include "xdma_channel_i.h" /* constants shared with buffer descriptor */
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#include "xbasic_types.h"
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#include "xstatus.h"
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#include "xversion.h"
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#include "xbuf_descriptor.h"
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/************************** Constant Definitions *****************************/
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/* the following constants provide access to the bit fields of the DMA control
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* register (DMACR)
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*/
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#define XDC_DMACR_SOURCE_INCR_MASK 0x80000000UL /* increment source address */
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#define XDC_DMACR_DEST_INCR_MASK 0x40000000UL /* increment dest address */
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#define XDC_DMACR_SOURCE_LOCAL_MASK 0x20000000UL /* local source address */
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#define XDC_DMACR_DEST_LOCAL_MASK 0x10000000UL /* local dest address */
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#define XDC_DMACR_SG_DISABLE_MASK 0x08000000UL /* scatter gather disable */
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#define XDC_DMACR_GEN_BD_INTR_MASK 0x04000000UL /* descriptor interrupt */
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#define XDC_DMACR_LAST_BD_MASK XDC_CONTROL_LAST_BD_MASK /* last buffer */
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/* descriptor */
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/* the following constants provide access to the bit fields of the DMA status
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* register (DMASR)
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*/
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#define XDC_DMASR_BUSY_MASK 0x80000000UL /* channel is busy */
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#define XDC_DMASR_BUS_ERROR_MASK 0x40000000UL /* bus error occurred */
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#define XDC_DMASR_BUS_TIMEOUT_MASK 0x20000000UL /* bus timeout occurred */
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#define XDC_DMASR_LAST_BD_MASK XDC_STATUS_LAST_BD_MASK /* last buffer */
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/* descriptor */
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#define XDC_DMASR_SG_BUSY_MASK 0x08000000UL /* scatter gather is busy */
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/* the following constants provide access to the bit fields of the interrupt
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* status register (ISR) and the interrupt enable register (IER), bit masks
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* match for both registers such that they are named IXR
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*/
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#define XDC_IXR_DMA_DONE_MASK 0x1UL /* dma operation done */
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#define XDC_IXR_DMA_ERROR_MASK 0x2UL /* dma operation error */
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#define XDC_IXR_PKT_DONE_MASK 0x4UL /* packet done */
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#define XDC_IXR_PKT_THRESHOLD_MASK 0x8UL /* packet count threshold */
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#define XDC_IXR_PKT_WAIT_BOUND_MASK 0x10UL /* packet wait bound reached */
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#define XDC_IXR_SG_DISABLE_ACK_MASK 0x20UL /* scatter gather disable
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acknowledge occurred */
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#define XDC_IXR_SG_END_MASK 0x40UL /* last buffer descriptor
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disabled scatter gather */
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#define XDC_IXR_BD_MASK 0x80UL /* buffer descriptor done */
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/**************************** Type Definitions *******************************/
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/*
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* the following structure contains data which is on a per instance basis
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* for the XDmaChannel component
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*/
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typedef struct XDmaChannelTag {
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XVersion Version; /* version of the driver */
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u32 RegBaseAddress; /* base address of registers */
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u32 IsReady; /* device is initialized and ready */
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XBufDescriptor *PutPtr; /* keep track of where to put into list */
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XBufDescriptor *GetPtr; /* keep track of where to get from list */
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XBufDescriptor *CommitPtr; /* keep track of where to commit in list */
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XBufDescriptor *LastPtr; /* keep track of the last put in the list */
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u32 TotalDescriptorCount; /* total # of descriptors in the list */
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u32 ActiveDescriptorCount; /* # of descriptors pointing to buffers
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* in the buffer descriptor list */
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} XDmaChannel;
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/***************** Macros (Inline Functions) Definitions *********************/
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/************************** Function Prototypes ******************************/
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XStatus XDmaChannel_Initialize(XDmaChannel * InstancePtr, u32 BaseAddress);
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u32 XDmaChannel_IsReady(XDmaChannel * InstancePtr);
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XVersion *XDmaChannel_GetVersion(XDmaChannel * InstancePtr);
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XStatus XDmaChannel_SelfTest(XDmaChannel * InstancePtr);
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void XDmaChannel_Reset(XDmaChannel * InstancePtr);
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/* Control functions */
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u32 XDmaChannel_GetControl(XDmaChannel * InstancePtr);
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void XDmaChannel_SetControl(XDmaChannel * InstancePtr, u32 Control);
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/* Status functions */
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u32 XDmaChannel_GetStatus(XDmaChannel * InstancePtr);
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void XDmaChannel_SetIntrStatus(XDmaChannel * InstancePtr, u32 Status);
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u32 XDmaChannel_GetIntrStatus(XDmaChannel * InstancePtr);
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void XDmaChannel_SetIntrEnable(XDmaChannel * InstancePtr, u32 Enable);
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u32 XDmaChannel_GetIntrEnable(XDmaChannel * InstancePtr);
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/* DMA without scatter gather functions */
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void XDmaChannel_Transfer(XDmaChannel * InstancePtr,
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u32 * SourcePtr, u32 * DestinationPtr, u32 ByteCount);
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/* Scatter gather functions */
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XStatus XDmaChannel_SgStart(XDmaChannel * InstancePtr);
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XStatus XDmaChannel_SgStop(XDmaChannel * InstancePtr,
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XBufDescriptor ** BufDescriptorPtr);
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XStatus XDmaChannel_CreateSgList(XDmaChannel * InstancePtr,
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u32 * MemoryPtr, u32 ByteCount);
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u32 XDmaChannel_IsSgListEmpty(XDmaChannel * InstancePtr);
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XStatus XDmaChannel_PutDescriptor(XDmaChannel * InstancePtr,
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XBufDescriptor * BufDescriptorPtr);
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XStatus XDmaChannel_CommitPuts(XDmaChannel * InstancePtr);
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XStatus XDmaChannel_GetDescriptor(XDmaChannel * InstancePtr,
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XBufDescriptor ** BufDescriptorPtr);
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/* Packet functions for interrupt collescing */
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u32 XDmaChannel_GetPktCount(XDmaChannel * InstancePtr);
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void XDmaChannel_DecrementPktCount(XDmaChannel * InstancePtr);
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XStatus XDmaChannel_SetPktThreshold(XDmaChannel * InstancePtr, u8 Threshold);
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u8 XDmaChannel_GetPktThreshold(XDmaChannel * InstancePtr);
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void XDmaChannel_SetPktWaitBound(XDmaChannel * InstancePtr, u32 WaitBound);
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u32 XDmaChannel_GetPktWaitBound(XDmaChannel * InstancePtr);
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#endif /* end of protection macro */
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