345 lines
9.8 KiB
C
345 lines
9.8 KiB
C
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#ifndef I2O_H
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#define I2O_H
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/*********************************************************
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*
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* copyright @ Motorola, 1999
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*********************************************************/
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#define I2O_REG_OFFSET 0x0004
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#define PCI_CFG_CLA 0x0B
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#define PCI_CFG_SCL 0x0A
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#define PCI_CFG_PIC 0x09
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#define I2O_IMR0 0x0050
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#define I2O_IMR1 0x0054
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#define I2O_OMR0 0x0058
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#define I2O_OMR1 0x005C
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#define I2O_ODBR 0x0060
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#define I2O_IDBR 0x0068
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#define I2O_OMISR 0x0030
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#define I2O_OMIMR 0x0034
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#define I2O_IMISR 0x0100
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#define I2O_IMIMR 0x0104
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/* accessable to PCI master but local processor */
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#define I2O_IFQPR 0x0040
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#define I2O_OFQPR 0x0044
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/* accessable to local processor */
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#define I2O_IFHPR 0x0120
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#define I2O_IFTPR 0x0128
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#define I2O_IPHPR 0x0130
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#define I2O_IPTPR 0x0138
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#define I2O_OFHPR 0x0140
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#define I2O_OFTPR 0x0148
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#define I2O_OPHPR 0x0150
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#define I2O_OPTPR 0x0158
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#define I2O_MUCR 0x0164
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#define I2O_QBAR 0x0170
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#define I2O_NUM_MSG 2
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typedef enum _i2o_status
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{
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I2OSUCCESS = 0,
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I2OINVALID,
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I2OMSGINVALID,
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I2ODBINVALID,
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I2OQUEINVALID,
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I2OQUEEMPTY,
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I2OQUEFULL,
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I2ONOEVENT,
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} I2OSTATUS;
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typedef enum _queue_size
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{
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QSIZE_4K = 0x02,
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QSIZE_8K = 0x04,
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QSIZE_16K = 0x08,
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QSIZE_32K = 0x10,
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QSIZe_64K = 0x20,
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} QUEUE_SIZE;
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typedef enum _location
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{
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LOCAL = 0, /* used by local processor to access its own on board device,
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local processor's eumbbar is required */
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REMOTE, /* used by PCI master to access the devices on its PCI device,
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device's pcsrbar is required */
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} LOCATION;
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/* door bell */
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typedef enum _i2o_in_db
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{
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IN_DB = 1,
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MC, /* machine check */
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} I2O_IN_DB;
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/* I2O PCI configuration identification */
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typedef struct _i2o_iop
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{
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unsigned int base_class : 8;
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unsigned int sub_class : 8;
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unsigned int prg_code : 8;
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} I2OIOP;
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/* I2O Outbound Message Interrupt Status Register */
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typedef struct _i2o_om_stat
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{
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unsigned int rsvd0 : 26;
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unsigned int opqi : 1;
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unsigned int rsvd1 : 1;
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unsigned int odi : 1;
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unsigned int rsvd2 : 1;
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unsigned int om1i : 1;
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unsigned int om0i : 1;
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} I2OOMSTAT;
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/* I2O inbound Message Interrupt Status Register */
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typedef struct _i2o_im_stat
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{
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unsigned int rsvd0 : 23;
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unsigned int ofoi : 1;
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unsigned int ipoi : 1;
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unsigned int rsvd1 : 1;
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unsigned int ipqi : 1;
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unsigned int mci : 1;
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unsigned int idi : 1;
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unsigned int rsvd2 : 1;
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unsigned int im1i : 1;
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unsigned int im0i : 1;
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} I2OIMSTAT;
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/**
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Enable the interrupt associated with in/out bound msg
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Inbound message interrupt generated by PCI master and serviced by local processor
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local processor needs to enable its inbound interrupts it wants to handle (LOCAL)
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Outbound message interrupt generated by local processor and serviced by PCI master
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PCI master needs to enable the devices' outbound interrupts it wants to handle (REMOTE)
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**/
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extern I2OSTATUS I2OMsgEnable( LOCATION, /* REMOTE/LOCAL */
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unsigned int base, /* pcsrbar/eumbbar */
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unsigned char n ); /* b'1' - msg 0
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* b'10'- msg 1
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* b'11'- both
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*/
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/**
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Disable the interrupt associated with in/out bound msg
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local processor needs to disable its inbound interrupts it is not interested (LOCAL)
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PCI master needs to disable outbound interrupts of devices it is not interested (REMOTE)
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**/
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extern I2OSTATUS I2OMsgDisable( LOCATION, /* REMOTE/LOCAL */
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unsigned int base, /* pcsrbar/eumbbar */
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unsigned char n ); /* b'1' - msg 0
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* b'10'- msg 1
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* b'11'- both
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*/
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/**
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Read the msg register either from local inbound msg 0/1,
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or an outbound msg 0/1 of devices.
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If it is not local, pcsrbar must be passed to the function.
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Otherwise eumbbar is passed.
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If it is remote, outbound msg of the device is read.
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Otherwise local inbound msg is read.
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**/
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extern I2OSTATUS I2OMsgGet ( LOCATION, /* REMOTE/LOCAL */
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unsigned int base, /*pcsrbar/eumbbar */
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unsigned int n, /* 0 or 1 */
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unsigned int *msg );
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/**
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Write to nth Msg register either on local outbound msg 0/1,
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or aninbound msg 0/1 of devices
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If it is not local, pcsrbar must be passed to the function.
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Otherwise eumbbar is passed.
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If it is remote, inbound msg on the device is written.
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Otherwise local outbound msg is written.
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**/
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extern I2OSTATUS I2OMsgPost( LOCATION, /* REMOTE/LOCAL */
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unsigned int base, /*pcsrbar/eumbbar */
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unsigned int n, /* 0 or 1 */
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unsigned int msg );
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/**
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Enable the In/Out DoorBell Interrupt
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InDoorBell interrupt is generated by PCI master and serviced by local processor
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local processor needs to enable its inbound doorbell interrupts it wants to handle
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OutDoorbell interrupt is generated by local processor and serviced by PCI master
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PCI master needs to enable outbound doorbell interrupts of the devices it wants to handle
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**/
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extern I2OSTATUS I2ODBEnable( LOCATION, /* REMOTE/LOCAL */
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unsigned int base, /* pcsrbar/eumbbar */
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unsigned int in_db );/* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
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/**
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Disable the In/Out DoorBell Interrupt
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local processor needs to disable its inbound doorbell interrupts it is not interested
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PCI master needs to disable outbound doorbell interrupts of devices it is not interested
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**/
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extern I2OSTATUS I2ODBDisable( LOCATION, /* REMOTE/LOCAL */
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unsigned int base, /* pcsrbar/eumbbar */
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unsigned int in_db ); /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
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/**
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Read a local indoorbell register, or an outdoorbell of devices.
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Reading a doorbell register, the register will be cleared.
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If it is not local, pcsrbar must be passed to the function.
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Otherwise eumbbar is passed.
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If it is remote, outdoorbell register on the device is read.
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Otherwise local in doorbell is read
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**/
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extern unsigned int I2ODBGet( LOCATION, /* REMOTE/LOCAL */
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unsigned int base); /* pcsrbar/eumbbar */
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/**
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Write to a local outdoorbell register, or an indoorbell register of devices.
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If it is not local, pcsrbar must be passed to the function.
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Otherwise eumbbar is passed.
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If it is remote, in doorbell register on the device is written.
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Otherwise local out doorbell is written
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**/
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extern void I2ODBPost( LOCATION, /* REMOTE/LOCAL */
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unsigned int base, /* pcsrbar/eumbbar */
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unsigned int msg ); /* in / out */
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/**
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Read the outbound msg unit interrupt status of devices. Reading an interrupt status register,
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the register will be cleared.
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The outbound interrupt status is AND with the outbound
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interrupt mask. The result is returned.
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PCI master must pass the pcsrbar to the function.
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**/
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extern I2OSTATUS I2OOutMsgStatGet( unsigned int pcsrbar, I2OOMSTAT * );
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/**
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Read the inbound msg unit interrupt status. Reading an interrupt status register,
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the register will be cleared.
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The inbound interrupt status is AND with the inbound
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interrupt mask. The result is returned.
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Local process must pass its eumbbar to the function.
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**/
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extern I2OSTATUS I2OInMsgStatGet( unsigned int eumbbar, I2OIMSTAT * );
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/**
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Configure the I2O FIFO, including QBAR, IFHPR/IFTPR,IPHPR/IPTPR,OFHPR/OFTPR, OPHPR/OPTPR,
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MUCR.
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**/
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extern I2OSTATUS I2OFIFOInit( unsigned int eumbbar,
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QUEUE_SIZE,
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unsigned int qba);/* queue base address that must be aligned at 1M */
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/**
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Enable the circular queue
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**/
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extern I2OSTATUS I2OFIFOEnable( unsigned int eumbbar );
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/**
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Disable the circular queue
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**/
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extern void I2OFIFODisable( unsigned int eumbbar );
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/**
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Enable the circular queue interrupt
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PCI master enables outbound FIFO interrupt of device
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Device enables its inbound FIFO interrupt
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**/
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extern void I2OFIFOIntEnable( LOCATION, unsigned int base );
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/**
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Disable the circular queue interrupt
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PCI master disables outbound FIFO interrupt of device
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Device disables its inbound FIFO interrupt
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**/
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extern void I2OFIFOIntDisable( LOCATION, unsigned int base );
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/**
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Enable the circular queue overflow interrupt
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**/
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extern void I2OFIFOOverflowIntEnable( unsigned int eumbbar );
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/**
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Disable the circular queue overflow interrupt
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**/
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extern void I2OFIFOOverflowIntDisable( unsigned int eumbbar );
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/**
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Allocate a free msg frame from free FIFO.
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PCI Master allocates a free msg frame through inbound queue port of device(IFQPR)
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while local processor allocates a free msg frame from outbound free queue(OFTPR)
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Unless both free queues are initialized, allocating a free MF will return 0xffffffff
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**/
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extern I2OSTATUS I2OFIFOAlloc( LOCATION,
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unsigned int base,
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void **pMsg);
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/**
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Free a used msg frame back to free queue
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PCI Master frees a MFA through outbound queue port of device(OFQPR)
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while local processor frees a MFA into its inbound free queue(IFHPR)
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Used msg frame does not need to be recycled in the order they
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read
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This function has to be called by PCI master to initialize Inbound free queue
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and by device to initialize Outbound free queue before I2OFIFOAlloc can be used.
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**/
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extern I2OSTATUS I2OFIFOFree( LOCATION,
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unsigned int base,
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void *pMsg );
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/**
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Post a msg into FIFO
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PCI Master posts a msg through inbound queue port of device(IFQPR)
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while local processor post a msg into its outbound post queue(OPHPR)
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The total number of msg must be less than the max size of the queue
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Otherwise queue overflow interrupt will assert.
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**/
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extern I2OSTATUS I2OFIFOPost( LOCATION,
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unsigned int base,
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void *pMsg );
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/**
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Read a msg from FIFO
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PCI Master reads a msg through outbound queue port of device(OFQPR)
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while local processor reads a msg from its inbound post queue(IPTPR)
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**/
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extern I2OSTATUS I2OFIFOGet( LOCATION,
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unsigned int base,
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void **pMsg );
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/**
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Get the I2O PCI configuration identification register
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**/
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extern I2OSTATUS I2OPCIConfigGet( LOCATION,
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unsigned int base,
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I2OIOP *);
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#endif
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