161 lines
6.2 KiB
C
161 lines
6.2 KiB
C
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/*
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* include/asm-armnommu/arch-netarm/netarm_eth_module.h
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*
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* Copyright (C) 2000 NETsilicon, Inc.
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* Copyright (C) 2000 WireSpeed Communications Corporation
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*
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* This software is copyrighted by WireSpeed. LICENSEE agrees that
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* it will not delete this copyright notice, trademarks or protective
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* notices from any copy made by LICENSEE.
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*
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* This software is provided "AS-IS" and any express or implied
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* warranties or conditions, including but not limited to any
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* implied warranties of merchantability and fitness for a particular
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* purpose regarding this software. In no event shall WireSpeed
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* be liable for any indirect, consequential, or incidental damages,
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* loss of profits or revenue, loss of use or data, or interruption
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* of business, whether the alleged damages are labeled in contract,
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* tort, or indemnity.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* author(s) : Jackie Smith Cashion
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* David Smith
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*/
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#ifndef __NETARM_ETH_MODULE_REGISTERS_H
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#define __NETARM_ETH_MODULE_REGISTERS_H
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/* ETH unit register offsets */
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#define NETARM_ETH_MODULE_BASE (0xFF800000)
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#define get_eth_reg_addr(c) ((volatile unsigned int *)(NETARM_ETH_MODULE_BASE + (c)))
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#define NETARM_ETH_GEN_CTRL (0x000) /* Ethernet Gen Control Reg */
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#define NETARM_ETH_GEN_STAT (0x004) /* Ethernet Gen Status Reg */
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#define NETARM_ETH_FIFO_DAT1 (0x008) /* Fifo Data Reg 1 */
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#define NETARM_ETH_FIFO_DAT2 (0x00C) /* Fifo Data Reg 2 */
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#define NETARM_ETH_TX_STAT (0x010) /* Transmit Status Reg */
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#define NETARM_ETH_RX_STAT (0x014) /* Receive Status Reg */
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#define NETARM_ETH_MAC_CFG (0x400) /* MAC Configuration Reg */
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#define NETARM_ETH_PCS_CFG (0x408) /* PCS Configuration Reg */
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#define NETARM_ETH_STL_CFG (0x410) /* STL Configuration Reg */
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#define NETARM_ETH_B2B_IPG_GAP_TMR (0x440) /* Back-to-back IPG
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Gap Timer Reg */
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#define NETARM_ETH_NB2B_IPG_GAP_TMR (0x444) /* Non Back-to-back
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IPG Gap Timer Reg */
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#define NETARM_ETH_MII_CMD (0x540) /* MII (PHY) Command Reg */
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#define NETARM_ETH_MII_ADDR (0x544) /* MII Address Reg */
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#define NETARM_ETH_MII_WRITE (0x548) /* MII Write Data Reg */
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#define NETARM_ETH_MII_READ (0x54C) /* MII Read Data Reg */
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#define NETARM_ETH_MII_IND (0x550) /* MII Indicators Reg */
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#define NETARM_ETH_MIB_CRCEC (0x580) /* (MIB) CRC Error Counter */
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#define NETARM_ETH_MIB_AEC (0x584) /* Alignment Error Counter */
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#define NETARM_ETH_MIB_CEC (0x588) /* Code Error Counter */
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#define NETARM_ETH_MIB_LFC (0x58C) /* Long Frame Counter */
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#define NETARM_ETH_MIB_SFC (0x590) /* Short Frame Counter */
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#define NETARM_ETH_MIB_LCC (0x594) /* Late Collision Counter */
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#define NETARM_ETH_MIB_EDC (0x598) /* Excessive Deferral
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Counter */
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#define NETARM_ETH_MIB_MCC (0x59C) /* Maximum Collision Counter */
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#define NETARM_ETH_SAL_FILTER (0x5C0) /* SAL Station Address
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Filter Reg */
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#define NETARM_ETH_SAL_STATION_ADDR_1 (0x5C4) /* SAL Station Address
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Reg */
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#define NETARM_ETH_SAL_STATION_ADDR_2 (0x5C8)
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#define NETARM_ETH_SAL_STATION_ADDR_3 (0x5CC)
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#define NETARM_ETH_SAL_HASH_TBL_1 (0x5D0) /* SAL Multicast Hash Table*/
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#define NETARM_ETH_SAL_HASH_TBL_2 (0x5D4)
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#define NETARM_ETH_SAL_HASH_TBL_3 (0x5D8)
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#define NETARM_ETH_SAL_HASH_TBL_4 (0x5DC)
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/* select bitfield defintions */
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/* Ethernet General Control Register (0xFF80_0000) */
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#define NETARM_ETH_GCR_ERX (0x80000000) /* Enable Receive FIFO */
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#define NETARM_ETH_GCR_ERXDMA (0x40000000) /* Enable Receive DMA */
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#define NETARM_ETH_GCR_ETX (0x00800000) /* Enable Transmit FIFO */
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#define NETARM_ETH_GCR_ETXDMA (0x00400000) /* Enable Transmit DMA */
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#define NETARM_ETH_GCR_ETXWM_50 (0x00100000) /* Transmit FIFO Water
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Mark. Start transmit
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when FIFO is 50%
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full. */
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#define NETARM_ETH_GCR_PNA (0x00000400) /* pSOS pNA Buffer
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Descriptor Format */
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/* Ethernet General Status Register (0xFF80_0004) */
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#define NETARM_ETH_GST_RXFDB (0x30000000)
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#define NETARM_ETH_GST_RXREGR (0x08000000) /* Receive Register
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Ready */
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#define NETARM_ETH_GST_RXFIFOH (0x04000000)
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#define NETARM_ETH_GST_RXBR (0x02000000)
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#define NETARM_ETH_GST_RXSKIP (0x01000000)
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#define NETARM_ETH_GST_TXBC (0x00020000)
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/* Ethernet Transmit Status Register (0xFF80_0010) */
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#define NETARM_ETH_TXSTAT_TXOK (0x00008000)
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/* Ethernet Receive Status Register (0xFF80_0014) */
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#define NETARM_ETH_RXSTAT_SIZE (0xFFFF0000)
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#define NETARM_ETH_RXSTAT_RXOK (0x00002000)
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/* PCS Configuration Register (0xFF80_0408) */
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#define NETARM_ETH_PCSC_NOCFR (0x1) /* Disable Ciphering */
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#define NETARM_ETH_PCSC_ENJAB (0x2) /* Enable Jabber Protection */
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#define NETARM_ETH_PCSC_CLKS_25M (0x0) /* 25 MHz Clock Speed Select */
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#define NETARM_ETH_PCSC_CLKS_33M (0x4) /* 33 MHz Clock Speed Select */
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/* STL Configuration Register (0xFF80_0410) */
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#define NETARM_ETH_STLC_RXEN (0x2) /* Enable Packet Receiver */
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#define NETARM_ETH_STLC_AUTOZ (0x4) /* Auto Zero Statistics */
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/* MAC Configuration Register (0xFF80_0400) */
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#define NETARM_ETH_MACC_HUGEN (0x1) /* Enable Unlimited Transmit
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Frame Sizes */
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#define NETARM_ETH_MACC_PADEN (0x4) /* Automatic Pad Fill Frames
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to 64 Bytes */
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#define NETARM_ETH_MACC_CRCEN (0x8) /* Append CRC to Transmit
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Frames */
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/* MII (PHY) Command Register (0xFF80_0540) */
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#define NETARM_ETH_MIIC_RSTAT (0x1) /* Single Scan for Read Data */
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/* MII Indicators Register (0xFF80_0550) */
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#define NETARM_ETH_MIII_BUSY (0x1) /* MII I/F Busy with
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Read/Write */
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/* SAL Station Address Filter Register (0xFF80_05C0) */
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#define NETARM_ETH_SALF_PRO (0x8) /* Enable Promiscuous Mode */
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#define NETARM_ETH_SALF_PRM (0x4) /* Accept All Multicast
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Packets */
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#define NETARM_ETH_SALF_PRA (0x2) /* Accept Mulitcast Packets
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using Hash Table */
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#define NETARM_ETH_SALF_BROAD (0x1) /* Accept All Broadcast
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Packets */
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#endif /* __NETARM_GEN_MODULE_REGISTERS_H */
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