453 lines
14 KiB
C
453 lines
14 KiB
C
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/*
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* (C) Copyright 2005
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* Wolfgang Denk <wd@denx.de>
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* Copyright 2004 Freescale Semiconductor.
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* (C) Copyright 2002,2003 Motorola,Inc.
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* Xianghua Xiao <X.Xiao@motorola.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* TQM85xx (8560/40/55/41) board configuration file
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* High Level Configuration Options */
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#define CONFIG_BOOKE 1 /* BOOKE */
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#define CONFIG_E500 1 /* BOOKE e500 family */
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#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
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#define CONFIG_PCI
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
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/*
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* Only MPC8540 doesn't have CPM module
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*/
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#ifndef CONFIG_MPC8540
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#define CONFIG_CPM2 1 /* has CPM2 */
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#endif
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/*
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* sysclk for MPC85xx
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*
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* Two valid values are:
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* 33000000
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* 66000000
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*
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* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
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* is likely the desired value here, so that is now the default.
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* The board, however, can run at 66MHz. In any event, this value
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* must match the settings of some switches. Details can be found
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* in the README.mpc85xxads.
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*/
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#ifndef CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_CLK_FREQ 33333333
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#endif
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
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#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
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#undef CFG_DRAM_TEST /* memory test, takes time */
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#define CFG_MEMTEST_START 0x00000000
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#define CFG_MEMTEST_END 0x10000000
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/*
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*/
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#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
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#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
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#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
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/*
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* DDR Setup
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*/
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#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
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#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
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#define CONFIG_ADD_RAM_INFO 1 /* print additional info*/
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#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
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/* TQM8540 & 8560 need DLL-override */
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#define CONFIG_DDR_DLL /* DLL fix needed */
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#define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */
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#endif /* defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) */
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#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
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#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
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#endif /* defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) */
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/*
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* Flash on the Local Bus
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*/
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#define CFG_FLASH0 0xFC000000
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#define CFG_FLASH1 0xF8000000
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#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 }
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#define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */
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#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */
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#define CFG_BR0_PRELIM 0xfc001801 /* port size 32bit */
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#define CFG_OR0_PRELIM 0xfc000040 /* 64MB Flash */
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#define CFG_BR1_PRELIM 0xf8001801 /* port size 32bit */
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#define CFG_OR1_PRELIM 0xfc000040 /* 64MB Flash */
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#define CFG_FLASH_CFI /* flash is CFI compat. */
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#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
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#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
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#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
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#define CFG_MAX_FLASH_SECT 512 /* sectors per device */
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#undef CFG_FLASH_CHECKSUM
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#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
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#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
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#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
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#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
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#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
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#define CONFIG_L1_INIT_RAM
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#define CFG_INIT_RAM_LOCK 1
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#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
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#define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */
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#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/
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#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
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/* Serial Port */
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#if defined(CONFIG_TQM8560)
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#define CONFIG_CONS_ON_SCC /* define if console on SCC */
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#undef CONFIG_CONS_NONE /* define if console on something else */
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#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
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#else
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#define CONFIG_CONS_INDEX 1
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#undef CONFIG_SERIAL_SOFTWARE_FIFO
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#define CFG_NS16550
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#define CFG_NS16550_SERIAL
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#define CFG_NS16550_REG_SIZE 1
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#define CFG_NS16550_CLK get_bus_freq(0)
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#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
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#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
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#endif /* CONFIG_TQM8560 */
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#define CONFIG_BAUDRATE 115200
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
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/* Use the HUSH parser */
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#define CFG_HUSH_PARSER
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#ifdef CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#endif
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/* I2C */
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#define CONFIG_HARD_I2C /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */
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/* I2C RTC */
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#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
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#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
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/* I2C EEPROM */
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/*
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* EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
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*/
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#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
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#define CFG_EEPROM_PAGE_WRITE_ENABLE
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
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#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
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/* I2C SYSMON (LM75) */
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#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
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#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
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#define CFG_DTT_MAX_TEMP 70
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#define CFG_DTT_LOW_TEMP -30
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#define CFG_DTT_HYSTERESIS 3
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/* RapidIO MMU */
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#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
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#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
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#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
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/*
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* General PCI
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* Addresses are mapped 1-1.
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*/
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#define CFG_PCI1_MEM_BASE 0x80000000
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#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
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#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
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#define CFG_PCI1_IO_BASE 0xe2000000
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#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
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#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
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#if defined(CONFIG_PCI)
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#define CONFIG_EEPRO100
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#undef CONFIG_TULIP
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#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
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#endif /* CONFIG_PCI */
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#define CONFIG_NET_MULTI 1
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_MPC85XX_TSEC1 1
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#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
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#define CONFIG_MPC85XX_TSEC2 1
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#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
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#define TSEC1_PHY_ADDR 2
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#define TSEC2_PHY_ADDR 1
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define FEC_PHY_ADDR 3
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#define FEC_PHYIDX 0
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#define CONFIG_HAS_ETH1
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#define CONFIG_HAS_ETH2
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/* Options are TSEC[0-1], FEC */
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#define CONFIG_ETHPRIME "TSEC0"
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#if defined(CONFIG_TQM8540)
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/*
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* TQM8540 has 3 ethernet ports. 2 TSEC's and one FEC.
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* The FEC port is connected on the same signals as the FCC3 port
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* of the TQM8560 to the baseboard (STK85xx Starterkit).
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*
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* On the STK85xx Starterkit the X47/X50 jumper has to be set to
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* a - d (X50.2 - 3) to enable the FEC port.
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*/
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#define CONFIG_MPC85XX_FEC 1
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#define CONFIG_MPC85XX_FEC_NAME "FEC"
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#endif
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#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
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/*
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* TQM8541/55 have 4 ethernet ports. 2 TSEC's and 2 FCC's. Only one FCC port
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* can be used at once, since only one FCC port is available on the STK85xx
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* Starterkit.
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*
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* To use this port you have to configure U-Boot to use the FCC port 1...2
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* and set the X47/X50 jumper to:
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* FCC1: a - b (X47.2 - X50.2)
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* FCC2: a - c (X50.2 - 1)
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*/
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#define CONFIG_ETHER_ON_FCC
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#define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */
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#endif
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#if defined(CONFIG_TQM8560)
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/*
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* TQM8560 has 5 ethernet ports. 2 TSEC's and 3 FCC's. Only one FCC port
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* can be used at once, since only one FCC port is available on the STK85xx
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* Starterkit.
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*
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* To use this port you have to configure U-Boot to use the FCC port 1...3
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* and set the X47/X50 jumper to:
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* FCC1: a - b (X47.2 - X50.2)
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* FCC2: a - c (X50.2 - 1)
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* FCC3: a - d (X50.2 - 3)
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*/
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#define CONFIG_ETHER_ON_FCC
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#define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */
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#endif
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#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
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#define CONFIG_ETHER_ON_FCC1
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#define CFG_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
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#define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
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#define CFG_CPMFCR_RAMTYPE 0
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#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
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#endif
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#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
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#define CONFIG_ETHER_ON_FCC2
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#define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
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#define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13)
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#define CFG_CPMFCR_RAMTYPE 0
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#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
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#endif
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#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
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#define CONFIG_ETHER_ON_FCC3
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#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
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#define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
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#define CFG_CPMFCR_RAMTYPE 0
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#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Environment
|
||
|
|
*/
|
||
|
|
#define CFG_ENV_IS_IN_FLASH 1
|
||
|
|
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000)
|
||
|
|
#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
|
||
|
|
#define CFG_ENV_SIZE 0x2000
|
||
|
|
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
|
||
|
|
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
|
||
|
|
|
||
|
|
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||
|
|
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||
|
|
|
||
|
|
#define CONFIG_TIMESTAMP /* Print image info with ts */
|
||
|
|
|
||
|
|
#if defined(CONFIG_PCI)
|
||
|
|
# define ADD_PCI_CMD (CFG_CMD_PCI)
|
||
|
|
#else
|
||
|
|
# define ADD_PCI_CMD 0
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||
|
|
CFG_CMD_DHCP | \
|
||
|
|
CFG_CMD_NFS | \
|
||
|
|
CFG_CMD_SNTP | \
|
||
|
|
ADD_PCI_CMD | \
|
||
|
|
CFG_CMD_I2C | \
|
||
|
|
CFG_CMD_DATE | \
|
||
|
|
CFG_CMD_EEPROM | \
|
||
|
|
CFG_CMD_DTT | \
|
||
|
|
CFG_CMD_MII | \
|
||
|
|
CFG_CMD_PING )
|
||
|
|
#include <cmd_confdefs.h>
|
||
|
|
|
||
|
|
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Miscellaneous configurable options
|
||
|
|
*/
|
||
|
|
#define CFG_LONGHELP /* undef to save memory */
|
||
|
|
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
|
||
|
|
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||
|
|
|
||
|
|
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||
|
|
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||
|
|
#else
|
||
|
|
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size */
|
||
|
|
#define CFG_MAXARGS 16 /* max number of command args */
|
||
|
|
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||
|
|
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
|
||
|
|
|
||
|
|
/*
|
||
|
|
* For booting Linux, the board info and command line data
|
||
|
|
* have to be in the first 8 MB of memory, since this is
|
||
|
|
* the maximum mapped by the Linux kernel during initialization.
|
||
|
|
*/
|
||
|
|
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||
|
|
|
||
|
|
/* Cache Configuration */
|
||
|
|
#define CFG_DCACHE_SIZE 32768
|
||
|
|
#define CFG_CACHELINE_SIZE 32
|
||
|
|
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||
|
|
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Internal Definitions
|
||
|
|
*
|
||
|
|
* Boot Flags
|
||
|
|
*/
|
||
|
|
#define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */
|
||
|
|
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||
|
|
|
||
|
|
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||
|
|
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
|
||
|
|
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||
|
|
#endif
|
||
|
|
|
||
|
|
|
||
|
|
#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
|
||
|
|
|
||
|
|
#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
|
||
|
|
|
||
|
|
#define CONFIG_PREBOOT "echo;" \
|
||
|
|
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||
|
|
"echo"
|
||
|
|
|
||
|
|
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
|
||
|
|
|
||
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||
|
|
CFG_BOOTFILE \
|
||
|
|
"netdev=eth0\0" \
|
||
|
|
"consdev=ttyS0\0" \
|
||
|
|
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||
|
|
"nfsroot=$serverip:$rootpath\0" \
|
||
|
|
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||
|
|
"addip=setenv bootargs $bootargs " \
|
||
|
|
"ip=$ipaddr:$serverip:$gatewayip:$netmask" \
|
||
|
|
":$hostname:$netdev:off panic=1\0" \
|
||
|
|
"addcons=setenv bootargs $bootargs " \
|
||
|
|
"console=$consdev,$baudrate\0" \
|
||
|
|
"flash_nfs=run nfsargs addip addcons;" \
|
||
|
|
"bootm $kernel_addr\0" \
|
||
|
|
"flash_self=run ramargs addip addcons;" \
|
||
|
|
"bootm $kernel_addr $ramdisk_addr\0" \
|
||
|
|
"net_nfs=tftp $loadaddr $bootfile;" \
|
||
|
|
"run nfsargs addip addcons;bootm\0" \
|
||
|
|
"rootpath=/opt/eldk/ppc_85xx\0" \
|
||
|
|
"kernel_addr=FE000000\0" \
|
||
|
|
"ramdisk_addr=FE100000\0" \
|
||
|
|
"load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0" \
|
||
|
|
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
|
||
|
|
"cp.b 100000 fffc0000 40000;" \
|
||
|
|
"setenv filesize;saveenv\0" \
|
||
|
|
"upd=run load;run update\0" \
|
||
|
|
""
|
||
|
|
#define CONFIG_BOOTCOMMAND "run flash_self"
|
||
|
|
|
||
|
|
#endif /* __CONFIG_H */
|