192 lines
7.3 KiB
C
192 lines
7.3 KiB
C
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/*
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* (C) Copyright 2002
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* High Level Configuration Options */
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#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
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#define CONFIG_XSENGINE 1
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#define CONFIG_MMC 1
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#define BOARD_POST_INIT 1
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
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#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
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#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
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#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
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#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
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#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
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#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
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#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
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#define CFG_DRAM_BASE 0xa0000000
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#define CFG_DRAM_SIZE 0x04000000
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/* FLASH organization */
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
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#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
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#define PHYS_FLASH_2 0x00000000 /* Flash Bank #2 */
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#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 127 KB sectors */
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#define CFG_FLASH_BASE PHYS_FLASH_1
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/*
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* JFFS2 partitions
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*/
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/* No command line, one static partition, whole device */
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#undef CONFIG_JFFS2_CMDLINE
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#define CONFIG_JFFS2_DEV "nor0"
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#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
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#define CONFIG_JFFS2_PART_OFFSET 0x00000000
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/* mtdparts command line support */
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/* Note: fake mtd_id used, no linux mtd map file */
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/*
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#define CONFIG_JFFS2_CMDLINE
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#define MTDIDS_DEFAULT "nor0=xsengine-0"
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#define MTDPARTS_DEFAULT "mtdparts=xsengine-0:256k(uboot),1m(kernel1),8m(kernel2)"
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*/
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/* Environment settings */
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#define CONFIG_ENV_OVERWRITE
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) /* Addr of Environment Sector (after monitor)*/
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#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE /* Size of the Environment Sector */
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#define CFG_ENV_SIZE 0x4000 /* 16kB Total Size of Environment Sector */
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/* timeout values are in ticks */
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#define CFG_FLASH_ERASE_TOUT (75*CFG_HZ) /* Timeout for Flash Erase */
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#define CFG_FLASH_WRITE_TOUT (50*CFG_HZ) /* Timeout for Flash Write */
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/* Size of malloc() pool */
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#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024)
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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/* Hardware drivers */
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#define CONFIG_DRIVER_SMC91111
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#define CONFIG_SMC91111_BASE 0x04000300
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#define CONFIG_SMC_USE_32_BIT 1
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/* select serial console configuration */
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#define CONFIG_FFUART 1
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_PING | CFG_CMD_JFFS2)
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_IPADDR 192.168.1.50
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#define CONFIG_SERVERIP 192.168.1.2
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#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS1,115200"
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#define CONFIG_CMDLINE_TAG
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/* Miscellaneous configurable options */
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#define CFG_HUSH_PARSER 1
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#define CFG_PROMPT_HUSH_PS2 "> "
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "XS-Engine u-boot> " /* Monitor Command Prompt */
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0xA0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0xA0800000 /* 4 ... 8 MB in DRAM */
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#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */
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#define CFG_MMC_BASE 0xF0000000
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#define CFG_LOAD_ADDR 0xA0000000 /* load kernel to this address */
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/* Stack sizes - The stack sizes are set up in start.S using the settings below */
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#define CONFIG_STACKSIZE (128*1024) /* regular stack */
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
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#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
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#endif
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/* GP set register */
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#define CFG_GPSR0_VAL 0x0000A000 /* CS1, PROG(FPGA) */
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#define CFG_GPSR1_VAL 0x00020000 /* nPWE */
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#define CFG_GPSR2_VAL 0x0000C000 /* CS2, CS3 */
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/* GP clear register */
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#define CFG_GPCR0_VAL 0x00000000
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#define CFG_GPCR1_VAL 0x00000000
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#define CFG_GPCR2_VAL 0x00000000
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/* GP direction register */
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#define CFG_GPDR0_VAL 0x0000A000 /* CS1, PROG(FPGA) */
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#define CFG_GPDR1_VAL 0x00022A80 /* nPWE, FFUART + BTUART pins */
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#define CFG_GPDR2_VAL 0x0000C000 /* CS2, CS3 */
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/* GP rising edge detect register */
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#define CFG_GRER0_VAL 0x00000000
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#define CFG_GRER1_VAL 0x00000000
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#define CFG_GRER2_VAL 0x00000000
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/* GP falling edge detect register */
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#define CFG_GFER0_VAL 0x00000000
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#define CFG_GFER1_VAL 0x00000000
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#define CFG_GFER2_VAL 0x00000000
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/* GP alternate function register */
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#define CFG_GAFR0_L_VAL 0x80000000 /* CS1 */
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#define CFG_GAFR0_U_VAL 0x00000010 /* RDY */
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#define CFG_GAFR1_L_VAL 0x09988050 /* FFUART + BTUART pins */
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#define CFG_GAFR1_U_VAL 0x00000008 /* nPWE */
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#define CFG_GAFR2_L_VAL 0xA0000000 /* CS2, CS3 */
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#define CFG_GAFR2_U_VAL 0x00000000
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#define CFG_PSSR_VAL 0x00000020 /* Power manager sleep status */
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#define CFG_CCCR_VAL 0x00000161 /* 100 MHz memory, 400 MHz CPU */
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#define CFG_CKEN_VAL 0x000000C0 /* BTUART and FFUART enabled */
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#define CFG_ICMR_VAL 0x00000000 /* No interrupts enabled */
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/* Memory settings */
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#define CFG_MSC0_VAL 0x25F425F0
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/* MDCNFG: SDRAM Configuration Register */
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#define CFG_MDCNFG_VAL 0x000009C9
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/* MDREFR: SDRAM Refresh Control Register */
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#define CFG_MDREFR_VAL 0x00018018
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/* MDMRS: Mode Register Set Configuration Register */
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#define CFG_MDMRS_VAL 0x00220022
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#endif /* __CONFIG_H */
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