184 lines
7.2 KiB
C
184 lines
7.2 KiB
C
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/*
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* (C) Copyright 2003
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* Gerry Hamel, geh@ti.com, Texas Instruments
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*
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* Based on
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* linux/drivers/usb/device/bi/omap.h
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* Register definitions for TI OMAP1510 USB bus interface driver
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*
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* Author: MontaVista Software, Inc.
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* source@mvista.com
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*
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* 2003 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#ifndef __USBDCORE_OMAP1510_H__
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#define __USBDCORE_OMAP1510_H__
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/*
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* 13.2 MPU Register Map
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*/
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/* Table 13-1. USB Function Module Registers (endpoint) */
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#define UDC_BASE 0xFFFB4000
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#define UDC_OFFSET(offset) (UDC_BASE + (offset))
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#define UDC_REV UDC_OFFSET(0x0) /* Revision */
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#define UDC_EP_NUM UDC_OFFSET(0x4) /* Endpoint selection */
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#define UDC_DATA UDC_OFFSET(0x08) /* Data */
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#define UDC_CTRL UDC_OFFSET(0x0C) /* Control */
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#define UDC_STAT_FLG UDC_OFFSET(0x10) /* Status flag */
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#define UDC_RXFSTAT UDC_OFFSET(0x14) /* Receive FIFO status */
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#define UDC_SYSCON1 UDC_OFFSET(0x18) /* System configuration 1 */
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#define UDC_SYSCON2 UDC_OFFSET(0x1C) /* System configuration 2 */
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#define UDC_DEVSTAT UDC_OFFSET(0x20) /* Device status */
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#define UDC_SOF UDC_OFFSET(0x24) /* Start of frame */
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#define UDC_IRQ_EN UDC_OFFSET(0x28) /* Interrupt enable */
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#define UDC_DMA_IRQ_EN UDC_OFFSET(0x2C) /* DMA interrupt enable */
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#define UDC_IRQ_SRC UDC_OFFSET(0x30) /* Interrupt source */
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#define UDC_EPN_STAT UDC_OFFSET(0x34) /* Endpoint interrupt status */
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#define UDC_DMAN_STAT UDC_OFFSET(0x3C) /* DMA endpoint interrupt status */
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/* IRQ_EN register fields */
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#define UDC_Sof_IE (1 << 7) /* Start-of-frame interrupt enabled */
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#define UDC_EPn_RX_IE (1 << 5) /* Receive endpoint interrupt enabled */
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#define UDC_EPn_TX_IE (1 << 4) /* Transmit endpoint interrupt enabled */
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#define UDC_DS_Chg_IE (1 << 3) /* Device state changed interrupt enabled */
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#define UDC_EP0_IE (1 << 0) /* EP0 transaction interrupt enabled */
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/* IRQ_SRC register fields */
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#define UDC_TXn_Done (1 << 10) /* Transmit DMA channel n done */
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#define UDC_RXn_Cnt (1 << 9) /* Receive DMA channel n transactions count */
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#define UDC_RXn_EOT (1 << 8) /* Receive DMA channel n end of transfer */
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#define UDC_SOF_Flg (1 << 7) /* Start-of-frame interrupt flag */
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#define UDC_EPn_RX (1 << 5) /* Endpoint n OUT transaction */
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#define UDC_EPn_TX (1 << 4) /* Endpoint n IN transaction */
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#define UDC_DS_Chg (1 << 3) /* Device state changed */
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#define UDC_Setup (1 << 2) /* Setup transaction */
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#define UDC_EP0_RX (1 << 1) /* EP0 OUT transaction */
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#define UDC_EP0_TX (1 << 0) /* EP0 IN transaction */
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/* DEVSTAT register fields, 14.2.9 */
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#define UDC_R_WK_OK (1 << 6) /* Remote wakeup granted */
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#define UDC_USB_Reset (1 << 5) /* USB reset signalling is active */
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#define UDC_SUS (1 << 4) /* Suspended state */
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#define UDC_CFG (1 << 3) /* Configured state */
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#define UDC_ADD (1 << 2) /* Addressed state */
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#define UDC_DEF (1 << 1) /* Default state */
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#define UDC_ATT (1 << 0) /* Attached state */
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/* SYSCON1 register fields */
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#define UDC_Cfg_Lock (1 << 8) /* Device configuration locked */
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#define UDC_Nak_En (1 << 4) /* NAK enable */
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#define UDC_Self_Pwr (1 << 2) /* Device is self-powered */
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#define UDC_Soff_Dis (1 << 1) /* Shutoff disabled */
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#define UDC_Pullup_En (1 << 0) /* External pullup enabled */
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/* SYSCON2 register fields */
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#define UDC_Rmt_Wkp (1 << 6) /* Remote wakeup */
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#define UDC_Stall_Cmd (1 << 5) /* Stall endpoint */
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#define UDC_Dev_Cfg (1 << 3) /* Device configured */
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#define UDC_Clr_Cfg (1 << 2) /* Clear configured */
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/*
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* Select and enable endpoints
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*/
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/* Table 13-1. USB Function Module Registers (endpoint configuration) */
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#define UDC_EPBASE UDC_OFFSET(0x80) /* Endpoints base address */
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#define UDC_EP0 UDC_EPBASE /* Control endpoint configuration */
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#define UDC_EP_RX_BASE UDC_OFFSET(0x84) /* Receive endpoints base address */
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#define UDC_EP_RX(endpoint) (UDC_EP_RX_BASE + ((endpoint) - 1) * 4)
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#define UDC_EP_TX_BASE UDC_OFFSET(0xC4) /* Transmit endpoints base address */
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#define UDC_EP_TX(endpoint) (UDC_EP_TX_BASE + ((endpoint) - 1) * 4)
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/* EP_NUM register fields */
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#define UDC_Setup_Sel (1 << 6) /* Setup FIFO select */
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#define UDC_EP_Sel (1 << 5) /* TX/RX FIFO select */
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#define UDC_EP_Dir (1 << 4) /* Endpoint direction */
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/* CTRL register fields */
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#define UDC_Clr_Halt (1 << 7) /* Clear halt endpoint */
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#define UDC_Set_Halt (1 << 6) /* Set halt endpoint */
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#define UDC_Set_FIFO_En (1 << 2) /* Set FIFO enable */
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#define UDC_Clr_EP (1 << 1) /* Clear endpoint */
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#define UDC_Reset_EP (1 << 0) /* Reset endpoint */
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/* STAT_FLG register fields */
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#define UDC_Miss_In (1 << 14)
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#define UDC_Data_Flush (1 << 13)
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#define UDC_ISO_Err (1 << 12)
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#define UDC_ISO_FIFO_Empty (1 << 9)
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#define UDC_ISO_FIFO_Full (1 << 8)
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#define UDC_EP_Halted (1 << 6)
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#define UDC_STALL (1 << 5)
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#define UDC_NAK (1 << 4)
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#define UDC_ACK (1 << 3)
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#define UDC_FIFO_En (1 << 2)
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#define UDC_Non_ISO_FIFO_Empty (1 << 1)
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#define UDC_Non_ISO_FIFO_Full (1 << 0)
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/* EPn_RX register fields */
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#define UDC_EPn_RX_Valid (1 << 15) /* valid */
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#define UDC_EPn_RX_Db (1 << 14) /* double-buffer */
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#define UDC_EPn_RX_Iso (1 << 11) /* isochronous */
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/* EPn_TX register fields */
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#define UDC_EPn_TX_Valid (1 << 15) /* valid */
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#define UDC_EPn_TX_Db (1 << 14) /* double-buffer */
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#define UDC_EPn_TX_Iso (1 << 11) /* isochronous */
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#define EP0_PACKETSIZE 0x40
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/* physical to logical endpoint mapping
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* Physical endpoints are an index into device->bus->endpoint_array.
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* Logical endpoints are endpoints 0 to 15 IN and OUT as defined in
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* the USB specification.
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*
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* physical ep logical ep direction endpoint_address
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* 0 0 IN and OUT 0x00
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* 1 to 15 1 to 15 OUT 0x01 to 0x0f
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* 16 to 30 1 to 15 IN 0x81 to 0x8f
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*/
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#define PHYS_EP_TO_EP_ADDR(ep) (((ep) < 16) ? (ep) : (((ep) - 15) | 0x80))
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#define EP_ADDR_TO_PHYS_EP(a) (((a) & 0x80) ? (((a) & ~0x80) + 15) : (a))
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/* MOD_CONF_CTRL_0 bits (FIXME: move to board hardware.h ?) */
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#define CONF_MOD_USB_W2FC_VBUS_MODE_R (1 << 17)
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/* Other registers (may be) related to USB */
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#define CLOCK_CTRL (0xFFFE0830)
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#define APLL_CTRL (0xFFFE084C)
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#define DPLL_CTRL (0xFFFE083C)
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#define SOFT_REQ (0xFFFE0834)
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#define STATUS_REQ (0xFFFE0840)
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/* FUNC_MUX_CTRL_0 bits related to USB */
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#define UDC_VBUS_CTRL (1 << 19)
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#define UDC_VBUS_MODE (1 << 18)
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void omap1510_udc_irq(void);
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void omap1510_udc_noniso_irq(void);
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/* Higher level functions for abstracting away from specific device */
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void udc_endpoint_write(struct usb_endpoint_instance *endpoint);
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int udc_init (void);
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void udc_enable(struct usb_device_instance *device);
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void udc_disable(void);
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void udc_connect(void);
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void udc_disconnect(void);
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void udc_startup_events(struct usb_device_instance *device);
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void udc_setup_ep(struct usb_device_instance *device, unsigned int ep, struct usb_endpoint_instance *endpoint);
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#endif
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