275 lines
11 KiB
C
275 lines
11 KiB
C
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/*
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* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/************************************************************************
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* config for XPedite1000 from XES Inc.
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* Ported from EBONY config by Travis B. Sawyer <tsawyer@sandburst.com>
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* (C) Copyright 2003 Sandburst Corporation
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* board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
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***********************************************************************/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*-----------------------------------------------------------------------
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* High Level Configuration Options
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*----------------------------------------------------------------------*/
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#define CONFIG_XPEDITE1K 1 /* Board is XPedite 1000 */
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#define CONFIG_440 1
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#define CONFIG_440GX 1 /* 440 GX */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
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#undef CFG_DRAM_TEST /* Disable-takes long time! */
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
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/* POST support */
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#define CONFIG_POST (CFG_POST_RTC | \
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CFG_POST_I2C)
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*----------------------------------------------------------------------*/
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#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
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#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */
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#define CFG_MONITOR_BASE CFG_FLASH_BASE /* start of monitor */
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#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
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#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
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#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
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#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
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#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
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#define CFG_GPIO_BASE (CFG_PERIPHERAL_BASE + 0x00000700)
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#define USR_LED0 0x00000080
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#define USR_LED1 0x00000100
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#define USR_LED2 0x00000200
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#define USR_LED3 0x00000400
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#ifndef __ASSEMBLY__
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extern unsigned long in32(unsigned int);
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extern void out32(unsigned int, unsigned long);
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#define LED0_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED0))
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#define LED1_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED1))
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#define LED2_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED2))
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#define LED3_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED3))
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#define LED0_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED0))
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#define LED1_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED1))
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#define LED2_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED2))
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#define LED3_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED3))
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#endif
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/*-----------------------------------------------------------------------
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* Initial RAM & stack pointer (placed in internal SRAM)
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*----------------------------------------------------------------------*/
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#define CFG_TEMP_STACK_OCM 1
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#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
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#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
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#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
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#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
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#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
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/*-----------------------------------------------------------------------
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* Serial Port
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*----------------------------------------------------------------------*/
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#undef CONFIG_SERIAL_SOFTWARE_FIFO
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#define CONFIG_BAUDRATE 9600
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
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/*-----------------------------------------------------------------------
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* NVRAM/RTC
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*
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* NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
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* The DS1743 code assumes this condition (i.e. -- it assumes the base
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* address for the RTC registers is:
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*
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* CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
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*
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*----------------------------------------------------------------------*/
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/* TBS: Xpedite 1000 has STMicro M41T00 via IIC */
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#define CONFIG_RTC_M41T11 1
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#define CFG_I2C_RTC_ADDR 0x68
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#define CFG_M41T11_BASE_YEAR 2000
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/*-----------------------------------------------------------------------
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* FLASH related
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*----------------------------------------------------------------------*/
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#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
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#define CFG_MAX_FLASH_SECT 8 /* sectors per device */
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#undef CFG_FLASH_CHECKSUM
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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/*-----------------------------------------------------------------------
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* DDR SDRAM
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*----------------------------------------------------------------------*/
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
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#define SPD_EEPROM_ADDRESS {0x54} /* SPD i2c spd addresses */
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#define CONFIG_VERY_BIG_RAM 1
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/*-----------------------------------------------------------------------
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* I2C
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*----------------------------------------------------------------------*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7f
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#define CFG_I2C_NOPROBES {0x55,0x56,0x57,0x58,0x59,0x5a,0x5b,0x5c,0x69} /* Don't probe these addrs */
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/*-----------------------------------------------------------------------
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* Environment
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*----------------------------------------------------------------------*/
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#define CFG_ENV_IS_IN_EEPROM 1
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#define CFG_ENV_SIZE 0x100 /* Size of Environment vars */
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#define CFG_ENV_OFFSET 0x100
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#define CFG_I2C_EEPROM_ADDR 0x50 /* this is actually the second page of the eeprom */
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#define CFG_I2C_EEPROM_ADDR_LEN 1
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#define CFG_EEPROM_PAGE_WRITE_ENABLE
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#define CFG_EEPROM_PAGE_WRITE_BITS 3
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
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#define CONFIG_BOOTARGS "root=/dev/hda1 "
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#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
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#define CONFIG_BOOTDELAY 5 /* disable autoboot */
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#define CONFIG_BAUDRATE 9600
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 0 /* PHY address phy0 not populated */
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#define CONFIG_PHY1_ADDR 1 /* PHY address phy1 not populated */
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#define CONFIG_PHY2_ADDR 4 /* PHY address phy2 */
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#define CONFIG_PHY3_ADDR 8 /* PHY address phy3 */
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#define CONFIG_NET_MULTI 1
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#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
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#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
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#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
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#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
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#define CONFIG_HAS_ETH2 1 /* add support for "eth2addr" */
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#define CONFIG_HAS_ETH3 1 /* add support for "eth3addr" */
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
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CFG_CMD_PCI | \
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CFG_CMD_IRQ | \
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CFG_CMD_I2C | \
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CFG_CMD_DATE | \
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CFG_CMD_BEDBUG | \
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CFG_CMD_EEPROM | \
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CFG_CMD_PING | \
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CFG_CMD_ELF | \
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CFG_CMD_MII | \
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CFG_CMD_DIAG | \
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CFG_CMD_FAT )
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/* CFG_CMD_DHCP | \ */
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/* CFG_CMD_KGDB | \ */
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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/* General PCI */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
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/* Board-specific PCI */
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#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
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#define CFG_PCI_TARGET_INIT /* let board init pci target */
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#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
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#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
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#define CFG_PCI_FORCE_PCI_CONV /* Force PCI Conventional Mode */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_DCACHE_SIZE 8192 /* For AMCC 440GX CPUs */
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#define CFG_CACHELINE_SIZE 32 /* ... */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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#endif /* __CONFIG_H */
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