251 lines
6.9 KiB
ArmAsm
251 lines
6.9 KiB
ArmAsm
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/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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*******************************************************************************/
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#define MV_ASMLANGUAGE
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#include "mvSysHwConfig.h"
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#include "mvBoardEnvSpec.h"
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#include "mvOsAsm.h"
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#include "pci/mvPciRegs.h"
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#include "pex/mvPexRegs.h"
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#include "mvCtrlEnvSpec.h"
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#include "mvCtrlEnvAsm.h"
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#include "sys/mvCpuIfRegs.h"
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jumpStart:
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.section ".reset_vector_sect",#alloc, #execinstr
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#if defined(MV_88F6082) || defined(MV_88F6183) || defined(DB_88F5181_OLD) || defined(DB_FPGA) || \
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defined(MV88F6281) || defined(MV88F6192) || defined(MV88F6180) || defined(MV_88F6183L) || \
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defined(MV88F6190)
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#if defined(__BE)
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/* disable I-Cache */
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.word 0x100f11ee /* mrc 15, 0, r0, cr1, cr0, {0} */
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.word 0x010ac0e3 /* bic r0, r0, #4096 ; 0x1000 */
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.word 0x0700c0e3 /* bic r0, r0, #7 ; 0x7 */
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.word 0x020080e3 /* orr r0, r0, #2 ; 0x2 */
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.word 0x100f01ee /* mcr 15, 0, r0, cr1, cr0, {0} */
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/* disable L2 prefetch */
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.word 0x110f3fee /* mrc p15, 1, r0, c15, c1 */
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.word 0x010480e3 /* orr r0, r0, #(1<<24) */
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.word 0x110f2fee /* mcr p15, 1, r0, c15, c1 */
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/* convert CPU to big endian */
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.word 0x100f11ee /* mrc p15, 0, r0, c1, c0 */
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.word 0x800080e3 /* orr r0, r0, #0x80 */
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.word 0x100f01ee /* mcr p15, 0, r0, c1, c0 */
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nop;nop;nop;nop;
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nop;nop;nop;nop;
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#endif
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#endif
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/* Check if we booted from DRAM. If we did someone already */
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/* initialize the DRAM controller */
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adr r4, jumpStart /* r4 <- current position of code */
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ldr r5, =~0xff
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and r4, r4, r5
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ldr r5, __start /* r5 <- linker results for _start */
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ldr r2, _jumpStart /* r2 <- linker results reset vector */
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sub r8, r2, r5 /* r8 <- (reset vector address - start address) */
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sub r8, r4, r8 /* r8 <- absolute address to jump to */
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/* r8 <- (current code address - */
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ldr sp, =0
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ldr lr, =0
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ldr r5, =CFG_RESET_ADDRESS /* test if we run from flash or RAM */
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cmp r4, r5 /* don't reloc during debug */
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beq romBoot
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mov r5, #1
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ldr r4, =dramBoot
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str r5, [r4] /* We started executing from DRAM */
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romBoot:
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#if defined(MV78200)
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/* Setting the PEX header device ID for MV78200 */
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MV_DV_REG_READ_ASM(r6, r1, PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID))
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ldr r1, =MV_78200_DEV_ID
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ldr r2, =0xffff
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and r6, r6, r2
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orr r6, r6, r1, LSL #PXDAVI_DEV_ID_OFFS
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MV_DV_REG_WRITE_ASM(r6, r1, PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID))
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#endif
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#if defined(MV_88F1181)
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/* set gpp out en */
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ldr r2, = 0xf33
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MV_DV_REG_WRITE_ASM(r1, r1, 0x10104)
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/* turn on debug led to 2 */
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ldr r2, = 0x8
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MV_DV_REG_WRITE_ASM(r1, r1, 0x10100)
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ldr pc, = 0xfff90000
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#else
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#if defined(DB_FPGA)
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b device_cont
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#endif /* DB_FPGA */
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/* Read device ID */
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MV_DV_CTRL_MODEL_GET_ASM(r6, r1);
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ldr r1, =0x5281
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cmp r6, r1
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beq device_5281
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/* TC90 acts as Orion 2 C0 */
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ldr r1, =0x1281
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cmp r6, r1
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beq device_5281_C0
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/* 6183 & 6183L */
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ldr r1, =0x6183
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cmp r6, r1
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bne device_cont
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#if defined(MV_88F6183L)
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/* Setting the PEX header device ID for 6183L */
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MV_DV_REG_READ_ASM(r6, r1, PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID))
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ldr r1, =MV_6183L_DEV_ID
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ldr r2, =0xffff
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and r6, r6, r2
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orr r6, r6, r1, LSL #PXDAVI_DEV_ID_OFFS
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MV_DV_REG_WRITE_ASM(r6, r1, PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID))
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#endif /* MV_88F6183L */
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/* Read device revision */
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MV_DV_CTRL_REV_GET_ASM(r6, r1);
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cmp r6, #0x3 /* 6183 == B0 */
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bne device_cont
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#if !defined(MV78XX0)
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MV_DV_REG_READ_ASM (r6, r1, CPU_FTDLL_CONFIG_REG)
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ldr r1, =0x10000
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orr r6, r6, r1
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MV_DV_REG_WRITE_ASM (r6, r1, CPU_FTDLL_CONFIG_REG)
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#endif
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b device_cont
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device_5281:
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/* Read device revision */
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MV_DV_CTRL_REV_GET_ASM(r6, r1);
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cmp r6, #0x0 /* Orion 2 == A0 */
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beq device_5281_A0
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cmp r6, #0x1 /* Orion 2 == B0 */
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beq device_5281_B0
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cmp r6, #0x2 /* Orion 2 == C0 */
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beq device_5281_C0
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cmp r6, #0x4 /* Orion 2 == d0 */
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beq device_5281_D0
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cmp r6, #0x5 /* Orion 2 == d1 */
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beq device_5281_D1
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cmp r6, #0x6 /* Orion 2 == d2 */
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beq device_5281_D2
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b device_cont
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device_5281_D0:
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device_5281_D1:
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device_5281_D2:
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#if !defined(MV78XX0)
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MV_DV_REG_READ_ASM (r6, r1, CPU_FTDLL_CONFIG_REG)
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ldr r1, =0xFFFF8080
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and r6, r6, r1
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ldr r1, =0x1902
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orr r6, r6, r1
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MV_DV_REG_WRITE_ASM (r6, r1, CPU_FTDLL_CONFIG_REG)
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#endif
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b device_cont
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device_5281_C0:
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#if !defined(MV78XX0)
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MV_DV_REG_READ_ASM (r6, r1, CPU_FTDLL_CONFIG_REG)
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ldr r1, =0xFFFF8080
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and r6, r6, r1
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ldr r1, =0x8308
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orr r6, r6, r1
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MV_DV_REG_WRITE_ASM (r6, r1, CPU_FTDLL_CONFIG_REG)
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#endif
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b device_cont
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device_5281_B0:
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#if !defined(MV78XX0)
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MV_DV_REG_READ_ASM (r6, r1, CPU_FTDLL_CONFIG_REG)
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ldr r1, =0xFFFF8080
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and r6, r6, r1
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ldr r1, =0x821b
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orr r6, r6, r1
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MV_DV_REG_WRITE_ASM (r6, r1, CPU_FTDLL_CONFIG_REG)
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#endif
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b device_cont
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device_5281_A0:
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device_cont:
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#if defined(MV88F6190)
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/* Setting the PEX header device ID for 6190 */
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MV_DV_REG_READ_ASM(r6, r1, PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID))
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ldr r1, =MV_6190_DEV_ID
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ldr r2, =0xffff
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and r6, r6, r2
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orr r6, r6, r1, LSL #PXDAVI_DEV_ID_OFFS
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MV_DV_REG_WRITE_ASM(r6, r1, PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID))
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#endif /* MV_88F6190 */
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mov lr, r8
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mov pc, lr
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#endif
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__start:
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.word _start
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.globl dramBoot
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dramBoot:
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.word 0
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_jumpStart:
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.word .reset_vector_sect
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.section ".dummy",#alloc, #execinstr
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.long 0xffffffff
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.long 0xffffffff
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.long 0xffffffff
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.long 0xffffffff
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