600 lines
11 KiB
C
600 lines
11 KiB
C
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/*
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* MPC8260 Internal Memory Map
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* Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
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*
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* The Internal Memory Map of the 8260. I don't know how generic
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* this will be, as I don't have any knowledge of the subsequent
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* parts at this time. I copied this from the 8xx_immap.h.
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*/
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#ifndef __IMMAP_82XX__
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#define __IMMAP_82XX__
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/* System configuration registers.
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*/
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typedef struct sys_conf {
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uint sc_siumcr;
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uint sc_sypcr;
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char res1[6];
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ushort sc_swsr;
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char res2[20];
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uint sc_bcr;
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u_char sc_ppc_acr;
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char res3[3];
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uint sc_ppc_alrh;
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uint sc_ppc_alrl;
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u_char sc_lcl_acr;
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char res4[3];
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uint sc_lcl_alrh;
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uint sc_lcl_alrl;
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uint sc_tescr1;
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uint sc_tescr2;
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uint sc_ltescr1;
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uint sc_ltescr2;
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uint sc_pdtea;
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u_char sc_pdtem;
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char res5[3];
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uint sc_ldtea;
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u_char sc_ldtem;
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char res6[163];
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} sysconf8260_t;
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/* Memory controller registers.
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*/
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typedef struct mem_ctlr {
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uint memc_br0;
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uint memc_or0;
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uint memc_br1;
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uint memc_or1;
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uint memc_br2;
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uint memc_or2;
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uint memc_br3;
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uint memc_or3;
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uint memc_br4;
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uint memc_or4;
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uint memc_br5;
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uint memc_or5;
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uint memc_br6;
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uint memc_or6;
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uint memc_br7;
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uint memc_or7;
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uint memc_br8;
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uint memc_or8;
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uint memc_br9;
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uint memc_or9;
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uint memc_br10;
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uint memc_or10;
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uint memc_br11;
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uint memc_or11;
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char res1[8];
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uint memc_mar;
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char res2[4];
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uint memc_mamr;
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uint memc_mbmr;
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uint memc_mcmr;
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char res3[8];
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ushort memc_mptpr;
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char res4[2];
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uint memc_mdr;
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char res5[4];
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uint memc_psdmr;
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uint memc_lsdmr;
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u_char memc_purt;
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char res6[3];
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u_char memc_psrt;
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char res7[3];
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u_char memc_lurt;
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char res8[3];
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u_char memc_lsrt;
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char res9[3];
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uint memc_immr;
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uint memc_pcibr0;
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uint memc_pcibr1;
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char res10[16];
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uint memc_pcimsk0;
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uint memc_pcimsk1;
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char res11[52];
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} memctl8260_t;
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/* System Integration Timers.
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*/
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typedef struct sys_int_timers {
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char res1[32];
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ushort sit_tmcntsc;
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char res2[2];
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uint sit_tmcnt;
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char res3[4];
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uint sit_tmcntal;
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char res4[16];
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ushort sit_piscr;
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char res5[2];
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uint sit_pitc;
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uint sit_pitr;
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char res6[94];
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char res7[390];
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} sit8260_t;
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/* PCI
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*/
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typedef struct pci_config {
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uint pci_omisr;
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uint pci_ominr;
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char res1[8];
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uint pci_ifqpr;
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uint pci_ofqpr;
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char res2[8];
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uint pci_imr0;
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uint pci_imr1;
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uint pci_omr0;
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uint pci_omr1;
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uint pci_odr;
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char res3[4];
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uint pci_idr;
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char res4[20];
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uint pci_imisr;
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uint pci_imimr;
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char res5[24];
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uint pci_ifhpr;
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char res5_2[4];
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uint pci_iftpr;
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char res6[4];
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uint pci_iphpr;
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char res6_2[4];
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uint pci_iptpr;
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char res7[4];
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uint pci_ofhpr;
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char res7_2[4];
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uint pci_oftpr;
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char res8[4];
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uint pci_ophpr;
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char res8_2[4];
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uint pci_optpr;
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char res9[8];
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uint pci_mucr;
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char res10[8];
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uint pci_qbar;
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char res11[12];
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uint pci_dmamr0;
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uint pci_dmasr0;
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uint pci_dmacdar0;
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char res12[4];
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uint pci_dmasar0;
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char res13[4];
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uint pci_dmadar0;
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char res14[4];
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uint pci_dmabcr0;
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uint pci_dmandar0;
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char res15[88];
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uint pci_dmamr1;
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uint pci_dmasr1;
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uint pci_dmacdar1;
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char res16[4];
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uint pci_dmasar1;
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char res17[4];
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uint pci_dmadar1;
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char res18[4];
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uint pci_dmabcr1;
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uint pci_dmandar1;
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char res19[88];
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uint pci_dmamr2;
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uint pci_dmasr2;
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uint pci_dmacdar2;
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char res20[4];
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uint pci_dmasar2;
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char res21[4];
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uint pci_dmadar2;
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char res22[4];
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uint pci_dmabcr2;
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uint pci_dmandar2;
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char res23[88];
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uint pci_dmamr3;
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uint pci_dmasr3;
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uint pci_dmacdar3;
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char res24[4];
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uint pci_dmasar3;
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char res25[4];
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uint pci_dmadar3;
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char res26[4];
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uint pci_dmabcr3;
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uint pci_dmandar3;
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char res27[344];
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uint pci_potar0;
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char res28[4];
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uint pci_pobar0;
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char res29[4];
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uint pci_pocmr0;
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char res30[4];
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uint pci_potar1;
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char res31[4];
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uint pci_pobar1;
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char res32[4];
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uint pci_pocmr1;
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char res33[4];
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uint pci_potar2;
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char res34[4];
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uint pci_pobar2;
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char res35[4];
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uint pci_pocmr2;
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char res36[52];
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uint pci_ptcr;
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uint pci_gpcr;
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uint pci_gcr;
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uint pci_esr;
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uint pci_emr;
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uint pci_ecr;
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uint pci_eacr;
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char res37[4];
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uint pci_edcr;
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char res38[4];
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uint pci_eccr;
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char res39[44];
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uint pci_pitar1;
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char res40[4];
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uint pci_pibar1;
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char res41[4];
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uint pci_picmr1;
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char res42[4];
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uint pci_pitar0;
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char res43[4];
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uint pci_pibar0;
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char res44[4];
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uint pci_picmr0;
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char res45[4];
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uint pci_cfg_addr;
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uint pci_cfg_data;
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uint pci_int_ack;
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char res46[756];
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}pci8260_t;
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#define PISCR_PIRQ_MASK ((ushort)0xff00)
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#define PISCR_PS ((ushort)0x0080)
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#define PISCR_PIE ((ushort)0x0004)
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#define PISCR_PTF ((ushort)0x0002)
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#define PISCR_PTE ((ushort)0x0001)
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/* Interrupt Controller.
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*/
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typedef struct interrupt_controller {
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ushort ic_sicr;
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char res1[2];
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uint ic_sivec;
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uint ic_sipnrh;
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uint ic_sipnrl;
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uint ic_siprr;
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uint ic_scprrh;
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uint ic_scprrl;
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uint ic_simrh;
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uint ic_simrl;
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uint ic_siexr;
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char res2[88];
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} intctl8260_t;
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/* Clocks and Reset.
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*/
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typedef struct clk_and_reset {
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uint car_sccr;
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char res1[4];
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uint car_scmr;
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char res2[4];
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uint car_rsr;
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uint car_rmr;
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char res[104];
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} car8260_t;
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/* Input/Output Port control/status registers.
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* Names consistent with processor manual, although they are different
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* from the original 8xx names.......
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*/
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typedef struct io_port {
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uint iop_pdira;
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uint iop_ppara;
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uint iop_psora;
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uint iop_podra;
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uint iop_pdata;
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char res1[12];
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uint iop_pdirb;
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uint iop_pparb;
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uint iop_psorb;
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uint iop_podrb;
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uint iop_pdatb;
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char res2[12];
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uint iop_pdirc;
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uint iop_pparc;
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uint iop_psorc;
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uint iop_podrc;
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uint iop_pdatc;
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char res3[12];
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uint iop_pdird;
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uint iop_ppard;
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uint iop_psord;
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uint iop_podrd;
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uint iop_pdatd;
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char res4[12];
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} iop8260_t;
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/* Communication Processor Module Timers
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*/
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typedef struct cpm_timers {
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u_char cpmt_tgcr1;
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char res1[3];
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u_char cpmt_tgcr2;
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char res2[11];
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ushort cpmt_tmr1;
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ushort cpmt_tmr2;
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ushort cpmt_trr1;
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ushort cpmt_trr2;
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ushort cpmt_tcr1;
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ushort cpmt_tcr2;
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ushort cpmt_tcn1;
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ushort cpmt_tcn2;
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ushort cpmt_tmr3;
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ushort cpmt_tmr4;
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ushort cpmt_trr3;
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ushort cpmt_trr4;
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ushort cpmt_tcr3;
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ushort cpmt_tcr4;
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ushort cpmt_tcn3;
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ushort cpmt_tcn4;
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ushort cpmt_ter1;
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ushort cpmt_ter2;
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ushort cpmt_ter3;
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ushort cpmt_ter4;
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char res3[584];
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} cpmtimer8260_t;
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/* DMA control/status registers.
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*/
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typedef struct sdma_csr {
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char res0[24];
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u_char sdma_sdsr;
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char res1[3];
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u_char sdma_sdmr;
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char res2[3];
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u_char sdma_idsr1;
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char res3[3];
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u_char sdma_idmr1;
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char res4[3];
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u_char sdma_idsr2;
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char res5[3];
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u_char sdma_idmr2;
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char res6[3];
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u_char sdma_idsr3;
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char res7[3];
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u_char sdma_idmr3;
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char res8[3];
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u_char sdma_idsr4;
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char res9[3];
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u_char sdma_idmr4;
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char res10[707];
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} sdma8260_t;
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/* Fast controllers
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*/
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typedef struct fcc {
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uint fcc_gfmr;
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uint fcc_fpsmr;
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ushort fcc_ftodr;
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char res1[2];
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ushort fcc_fdsr;
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char res2[2];
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ushort fcc_fcce;
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char res3[2];
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ushort fcc_fccm;
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char res4[2];
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u_char fcc_fccs;
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char res5[3];
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u_char fcc_ftirr_phy[4];
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} fcc_t;
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||
|
|
|
||
|
|
/* Fast controllers continued
|
||
|
|
*/
|
||
|
|
typedef struct fcc_c {
|
||
|
|
uint fcc_firper;
|
||
|
|
uint fcc_firer;
|
||
|
|
uint fcc_firsr_hi;
|
||
|
|
uint fcc_firsr_lo;
|
||
|
|
u_char fcc_gfemr;
|
||
|
|
char res1[15];
|
||
|
|
} fcc_c_t;
|
||
|
|
|
||
|
|
/* TC Layer
|
||
|
|
*/
|
||
|
|
typedef struct tclayer {
|
||
|
|
ushort tc_tcmode;
|
||
|
|
ushort tc_cdsmr;
|
||
|
|
ushort tc_tcer;
|
||
|
|
ushort tc_rcc;
|
||
|
|
ushort tc_tcmr;
|
||
|
|
ushort tc_fcc;
|
||
|
|
ushort tc_ccc;
|
||
|
|
ushort tc_icc;
|
||
|
|
ushort tc_tcc;
|
||
|
|
ushort tc_ecc;
|
||
|
|
char res1[12];
|
||
|
|
} tclayer_t;
|
||
|
|
|
||
|
|
/* I2C
|
||
|
|
*/
|
||
|
|
typedef struct i2c {
|
||
|
|
u_char i2c_i2mod;
|
||
|
|
char res1[3];
|
||
|
|
u_char i2c_i2add;
|
||
|
|
char res2[3];
|
||
|
|
u_char i2c_i2brg;
|
||
|
|
char res3[3];
|
||
|
|
u_char i2c_i2com;
|
||
|
|
char res4[3];
|
||
|
|
u_char i2c_i2cer;
|
||
|
|
char res5[3];
|
||
|
|
u_char i2c_i2cmr;
|
||
|
|
char res6[331];
|
||
|
|
} i2c8260_t;
|
||
|
|
|
||
|
|
typedef struct scc { /* Serial communication channels */
|
||
|
|
uint scc_gsmrl;
|
||
|
|
uint scc_gsmrh;
|
||
|
|
ushort scc_psmr;
|
||
|
|
char res1[2];
|
||
|
|
ushort scc_todr;
|
||
|
|
ushort scc_dsr;
|
||
|
|
ushort scc_scce;
|
||
|
|
char res2[2];
|
||
|
|
ushort scc_sccm;
|
||
|
|
char res3;
|
||
|
|
u_char scc_sccs;
|
||
|
|
char res4[8];
|
||
|
|
} scc_t;
|
||
|
|
|
||
|
|
typedef struct smc { /* Serial management channels */
|
||
|
|
char res1[2];
|
||
|
|
ushort smc_smcmr;
|
||
|
|
char res2[2];
|
||
|
|
u_char smc_smce;
|
||
|
|
char res3[3];
|
||
|
|
u_char smc_smcm;
|
||
|
|
char res4[5];
|
||
|
|
} smc_t;
|
||
|
|
|
||
|
|
/* Serial Peripheral Interface.
|
||
|
|
*/
|
||
|
|
typedef struct im_spi {
|
||
|
|
ushort spi_spmode;
|
||
|
|
char res1[4];
|
||
|
|
u_char spi_spie;
|
||
|
|
char res2[3];
|
||
|
|
u_char spi_spim;
|
||
|
|
char res3[2];
|
||
|
|
u_char spi_spcom;
|
||
|
|
char res4[82];
|
||
|
|
} im_spi_t;
|
||
|
|
|
||
|
|
/* CPM Mux.
|
||
|
|
*/
|
||
|
|
typedef struct cpmux {
|
||
|
|
u_char cmx_si1cr;
|
||
|
|
char res1;
|
||
|
|
u_char cmx_si2cr;
|
||
|
|
char res2;
|
||
|
|
uint cmx_fcr;
|
||
|
|
uint cmx_scr;
|
||
|
|
u_char cmx_smr;
|
||
|
|
char res3;
|
||
|
|
ushort cmx_uar;
|
||
|
|
char res4[16];
|
||
|
|
} cpmux_t;
|
||
|
|
|
||
|
|
/* SIRAM control
|
||
|
|
*/
|
||
|
|
typedef struct siram {
|
||
|
|
ushort si_amr;
|
||
|
|
ushort si_bmr;
|
||
|
|
ushort si_cmr;
|
||
|
|
ushort si_dmr;
|
||
|
|
u_char si_gmr;
|
||
|
|
char res1;
|
||
|
|
u_char si_cmdr;
|
||
|
|
char res2;
|
||
|
|
u_char si_str;
|
||
|
|
char res3;
|
||
|
|
ushort si_rsr;
|
||
|
|
} siramctl_t;
|
||
|
|
|
||
|
|
typedef struct mcc {
|
||
|
|
ushort mcc_mcce;
|
||
|
|
char res1[2];
|
||
|
|
ushort mcc_mccm;
|
||
|
|
char res2[2];
|
||
|
|
u_char mcc_mccf;
|
||
|
|
char res3[7];
|
||
|
|
} mcc_t;
|
||
|
|
|
||
|
|
typedef struct comm_proc {
|
||
|
|
uint cp_cpcr;
|
||
|
|
uint cp_rccr;
|
||
|
|
char res1[14];
|
||
|
|
ushort cp_rter;
|
||
|
|
char res2[2];
|
||
|
|
ushort cp_rtmr;
|
||
|
|
ushort cp_rtscr;
|
||
|
|
char res3[2];
|
||
|
|
uint cp_rtsr;
|
||
|
|
char res4[12];
|
||
|
|
} cpm8260_t;
|
||
|
|
|
||
|
|
/* ...and the whole thing wrapped up....
|
||
|
|
*/
|
||
|
|
typedef struct immap {
|
||
|
|
/* Some references are into the unique and known dpram spaces,
|
||
|
|
* others are from the generic base.
|
||
|
|
*/
|
||
|
|
#define im_dprambase im_dpram1
|
||
|
|
u_char im_dpram1[16*1024];
|
||
|
|
char res1[16*1024];
|
||
|
|
u_char im_dpram2[4*1024];
|
||
|
|
char res2[8*1024];
|
||
|
|
u_char im_dpram3[4*1024];
|
||
|
|
char res3[16*1024];
|
||
|
|
|
||
|
|
sysconf8260_t im_siu_conf; /* SIU Configuration */
|
||
|
|
memctl8260_t im_memctl; /* Memory Controller */
|
||
|
|
sit8260_t im_sit; /* System Integration Timers */
|
||
|
|
pci8260_t im_pci; /* PCI Configuration */
|
||
|
|
intctl8260_t im_intctl; /* Interrupt Controller */
|
||
|
|
car8260_t im_clkrst; /* Clocks and reset */
|
||
|
|
iop8260_t im_ioport; /* IO Port control/status */
|
||
|
|
cpmtimer8260_t im_cpmtimer; /* CPM timers */
|
||
|
|
sdma8260_t im_sdma; /* SDMA control/status */
|
||
|
|
|
||
|
|
fcc_t im_fcc[3]; /* Three FCCs */
|
||
|
|
|
||
|
|
char res4[32];
|
||
|
|
fcc_c_t im_fcc_c[3]; /* Continued FCCs */
|
||
|
|
char res4a[32];
|
||
|
|
|
||
|
|
tclayer_t im_tclayer[8]; /* Eight TCLayers */
|
||
|
|
ushort tc_tcgsr;
|
||
|
|
ushort tc_tcger;
|
||
|
|
|
||
|
|
/* First set of baud rate generators.
|
||
|
|
*/
|
||
|
|
char res4b[236];
|
||
|
|
uint im_brgc5;
|
||
|
|
uint im_brgc6;
|
||
|
|
uint im_brgc7;
|
||
|
|
uint im_brgc8;
|
||
|
|
|
||
|
|
char res5[608];
|
||
|
|
|
||
|
|
i2c8260_t im_i2c; /* I2C control/status */
|
||
|
|
cpm8260_t im_cpm; /* Communication processor */
|
||
|
|
|
||
|
|
/* Second set of baud rate generators.
|
||
|
|
*/
|
||
|
|
uint im_brgc1;
|
||
|
|
uint im_brgc2;
|
||
|
|
uint im_brgc3;
|
||
|
|
uint im_brgc4;
|
||
|
|
|
||
|
|
scc_t im_scc[4]; /* Four SCCs */
|
||
|
|
smc_t im_smc[2]; /* Couple of SMCs */
|
||
|
|
im_spi_t im_spi; /* A SPI */
|
||
|
|
cpmux_t im_cpmux; /* CPM clock route mux */
|
||
|
|
siramctl_t im_siramctl1; /* First SI RAM Control */
|
||
|
|
mcc_t im_mcc1; /* First MCC */
|
||
|
|
siramctl_t im_siramctl2; /* Second SI RAM Control */
|
||
|
|
mcc_t im_mcc2; /* Second MCC */
|
||
|
|
|
||
|
|
char res6[1184];
|
||
|
|
|
||
|
|
ushort im_si1txram[256];
|
||
|
|
char res7[512];
|
||
|
|
ushort im_si1rxram[256];
|
||
|
|
char res8[512];
|
||
|
|
ushort im_si2txram[256];
|
||
|
|
char res9[512];
|
||
|
|
ushort im_si2rxram[256];
|
||
|
|
char res10[512];
|
||
|
|
char res11[4096];
|
||
|
|
} immap_t;
|
||
|
|
|
||
|
|
#endif /* __IMMAP_82XX__ */
|