391 lines
14 KiB
C
391 lines
14 KiB
C
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/*
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**=====================================================================
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**
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** Copyright (C) 2000, 2001, 2002, 2003
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** The LEOX team <team@leox.org>, http://www.leox.org
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**
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** LEOX.org is about the development of free hardware and software resources
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** for system on chip.
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**
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** Description: U-Boot port on the LEOX's ELPT860 CPU board
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** ~~~~~~~~~~~
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**
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**=====================================================================
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**
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** This program is free software; you can redistribute it and/or
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** modify it under the terms of the GNU General Public License as
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** published by the Free Software Foundation; either version 2 of
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** the License, or (at your option) any later version.
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**
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** This program is distributed in the hope that it will be useful,
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** but WITHOUT ANY WARRANTY; without even the implied warranty of
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** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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** GNU General Public License for more details.
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**
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** You should have received a copy of the GNU General Public License
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** along with this program; if not, write to the Free Software
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** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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** MA 02111-1307 USA
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**
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**=====================================================================
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC860 1 /* It's a MPC860, in fact a 860T CPU */
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#define CONFIG_MPC860T 1
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#define CONFIG_ELPT860 1 /* ...on a LEOX's ELPT860 CPU board */
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#undef CONFIG_8xx_CONS_SMC2
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#undef CONFIG_8xx_CONS_NONE
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#define CONFIG_CLOCKS_IN_MHZ 1 /* Clock passed to Linux (<2.4.5) in MHz */
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#define CONFIG_8xx_GCLK_FREQ 50000000 /* MPC860T runs at 50MHz */
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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/* BOOT arguments */
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#define CONFIG_PREBOOT \
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"echo;" \
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"echo Type \"run nfsboot\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"rootargs=setenv rootpath /tftp/${ipaddr}\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:eth0:off panic=1\0" \
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"ramboot=tftp 400000 /home/paugaml/pMulti;" \
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"run ramargs;bootm\0" \
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"nfsboot=tftp 400000 /home/paugaml/uImage;" \
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"run rootargs;run nfsargs;run addip;bootm\0" \
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""
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#define CONFIG_BOOTCOMMAND "run ramboot"
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#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
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#undef CONFIG_RTC_MPC8xx /* internal RTC MPC8xx unused */
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#define CONFIG_RTC_DS164x 1 /* RTC is a Dallas DS1646 */
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
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CFG_CMD_ASKENV | \
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CFG_CMD_DATE )
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "LEOX_elpt860: " /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
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#define CFG_LOAD_ADDR 0x00100000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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/*
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* Environment Variables and Storages
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*/
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#define CONFIG_ENV_OVERWRITE 1 /* Allow Overwrite of serial# & ethaddr */
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#undef CFG_ENV_IS_IN_NVRAM /* Environment is in NVRAM */
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#undef CFG_ENV_IS_IN_EEPROM /* Environment is in I2C EEPROM */
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#define CFG_ENV_IS_IN_FLASH 1 /* Environment is in FLASH */
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#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 bps */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CONFIG_ETHADDR 00:01:77:00:60:40
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#define CONFIG_IPADDR 192.168.0.30
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_SERVERIP 192.168.0.1
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#define CONFIG_GATEWAYIP 192.168.0.1
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CFG_IMMR 0xFF000000
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0x02000000
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#define CFG_NVRAM_BASE 0x03000000
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#if defined(CFG_ENV_IS_IN_FLASH)
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# if defined(DEBUG)
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# define CFG_MONITOR_LEN (320 << 10) /* Reserve 320 kB for Monitor */
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# else
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# define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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# endif
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#else
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# if defined(DEBUG)
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# define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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# else
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# define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
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# endif
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#endif
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#if defined(CFG_ENV_IS_IN_FLASH)
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# define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
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# define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
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#endif
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/*-----------------------------------------------------------------------
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* NVRAM organization
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*/
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#define CFG_NVRAM_BASE_ADDR CFG_NVRAM_BASE /* Base address of NVRAM area */
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#define CFG_NVRAM_SIZE ((128*1024)-8) /* clock regs resident in the */
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/* 8 top NVRAM locations */
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#if defined(CFG_ENV_IS_IN_NVRAM)
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# define CFG_ENV_ADDR CFG_NVRAM_BASE /* Base address of NVRAM area */
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# define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
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#endif
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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# define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#if defined(CONFIG_WATCHDOG)
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# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
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#else
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# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWP)
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#endif
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/*-----------------------------------------------------------------------
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* SUMCR - SIU Module Configuration 11-6
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*-----------------------------------------------------------------------
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* PCMCIA config., multi-function pin tri-state
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*/
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#define CFG_SIUMCR (SIUMCR_DBGC11)
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
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/*-----------------------------------------------------------------------
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* RTCSC - Real-Time Clock Status and Control Register 11-27
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*-----------------------------------------------------------------------
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* Once-per-Second Interrupt, Alarm Interrupt, RTC freezing enabled, RTC
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* enabled
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*/
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#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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*/
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#define CFG_PISCR (PISCR_PS | PISCR_PITF)
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
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*-----------------------------------------------------------------------
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* Reset PLL lock status sticky bit, timer expired status bit and timer
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* interrupt status bit - leave PLL multiplication factor unchanged !
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*/
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#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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*-----------------------------------------------------------------------
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* Set clock output, timebase and RTC source and divider,
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* power management and some other internal clocks
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*/
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#define SCCR_MASK SCCR_EBDF11
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#define CFG_SCCR (SCCR_TBS | \
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SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
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SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
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SCCR_DFALCD00)
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/*-----------------------------------------------------------------------
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* Chip Selects + SDRAM timings + Memory Periodic Timer Prescaler
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*-----------------------------------------------------------------------
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*
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*/
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#ifdef DEBUG
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# define CFG_DER 0xFFE7400F /* Debug Enable Register */
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#else
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# define CFG_DER 0
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#endif
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/*
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* Init Memory Controller:
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* ~~~~~~~~~~~~~~~~~~~~~~
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*
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* BR0 and OR0 (FLASH)
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*/
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#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
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/* used to re-map FLASH both when starting from SRAM or FLASH:
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* restrict access enough to keep SRAM working (if any)
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* but not too much to meddle with FLASH accesses
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*/
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#define CFG_PRELIM_OR_AM 0xFF000000 /* 16 MB between each CSx */
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/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 0, SCY = 8, EHTR = 0 */
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#define CFG_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_BI | OR_SCY_8_CLK)
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#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
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#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
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/*
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* BR1 and OR1 (SDRAM)
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*
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*/
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#define SDRAM_BASE1_PRELIM CFG_SDRAM_BASE /* SDRAM bank #0 */
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#define SDRAM_MAX_SIZE 0x02000000 /* 32 MB MAX for CS1 */
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/* SDRAM timing: */
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#define CFG_OR_TIMING_SDRAM 0x00000000
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#define CFG_OR1_PRELIM ((2 * CFG_PRELIM_OR_AM) | CFG_OR_TIMING_SDRAM )
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#define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
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/*
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* BR2 and OR2 (NVRAM)
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*
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*/
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#define NVRAM_BASE1_PRELIM CFG_NVRAM_BASE /* NVRAM bank #0 */
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#define NVRAM_MAX_SIZE 0x00020000 /* 128 KB MAX for CS2 */
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#define CFG_OR2_PRELIM 0xFFF80160
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#define CFG_BR2_PRELIM ((NVRAM_BASE1_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
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/*
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* Memory Periodic Timer Prescaler
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||
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*/
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||
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|
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||
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/* periodic timer for refresh */
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||
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#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
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||
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/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
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||
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#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
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#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
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||
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|
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||
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/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
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||
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#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
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||
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#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
|
||
|
|
|
||
|
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/*
|
||
|
|
* MAMR settings for SDRAM
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* 8 column SDRAM */
|
||
|
|
#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||
|
|
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||
|
|
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
||
|
|
/* 9 column SDRAM */
|
||
|
|
#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||
|
|
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||
|
|
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------------
|
||
|
|
* Internal Definitions
|
||
|
|
*-----------------------------------------------------------------------
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Boot Flags
|
||
|
|
*/
|
||
|
|
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||
|
|
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||
|
|
|
||
|
|
|
||
|
|
#endif /* __CONFIG_H */
|