192 lines
9.4 KiB
C
192 lines
9.4 KiB
C
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/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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This software file (the "File") is owned and distributed by Marvell
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International Ltd. and/or its affiliates ("Marvell") under the following
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alternative licensing terms. Once you have made an election to distribute the
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File under one of the following license alternatives, please (i) delete this
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introductory statement regarding license alternatives, (ii) delete the two
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license alternatives that you have not elected to use and (iii) preserve the
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Marvell copyright notice above.
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********************************************************************************
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Marvell Commercial License Option
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If you received this File from Marvell and you have entered into a commercial
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license agreement (a "Commercial License") with Marvell, the File is licensed
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to you under the terms of the applicable Commercial License.
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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********************************************************************************
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Marvell BSD License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File under the following licensing terms.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Marvell nor the names of its contributors may be
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used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#ifndef __INCmvUsbRegsh
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#define __INCmvUsbRegsh
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/*******************************************/
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/* USB ARC Core Registers */
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/*******************************************/
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#define MV_USB_CORE_ID_REG(dev) (USB_REG_BASE(dev) + 0x00)
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#define MV_USB_CORE_GENERAL_REG(dev) (USB_REG_BASE(dev) + 0x04)
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#define MV_USB_CORE_HOST_REG(dev) (USB_REG_BASE(dev) + 0x08)
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#define MV_USB_CORE_DEVICE_REG(dev) (USB_REG_BASE(dev) + 0x0C)
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#define MV_USB_CORE_TX_BUF_REG(dev) (USB_REG_BASE(dev) + 0x10)
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#define MV_USB_CORE_RX_BUF_REG(dev) (USB_REG_BASE(dev) + 0x14)
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#define MV_USB_CORE_TTTX_BUF_REG(dev) (USB_REG_BASE(dev) + 0x18)
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#define MV_USB_CORE_TTRX_BUF_REG(dev) (USB_REG_BASE(dev) + 0x1C)
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#define MV_USB_CORE_CAP_LENGTH_REG(dev) (USB_REG_BASE(dev) + 0x100)
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#define MV_USB_CORE_CAP_HCS_PARAMS_REG(dev) (USB_REG_BASE(dev) + 0x104)
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#define MV_USB_CORE_CAP_HCC_PARAMS_REG(dev) (USB_REG_BASE(dev) + 0x108)
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#define MV_USB_CORE_CAP_DCI_VERSION_REG(dev) (USB_REG_BASE(dev) + 0x120)
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#define MV_USB_CORE_CAP_DCC_PARAMS_REG(dev) (USB_REG_BASE(dev) + 0x124)
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#define MV_USB_CORE_CMD_REG(dev) (USB_REG_BASE(dev) + 0x140)
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#define MV_USB_CORE_CMD_RUN_BIT 0
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#define MV_USB_CORE_CMD_RUN_MASK (1 << MV_USB_CORE_CMD_RUN_BIT)
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#define MV_USB_CORE_CMD_RESET_BIT 1
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#define MV_USB_CORE_CMD_RESET_MASK (1 << MV_USB_CORE_CMD_RESET_BIT)
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#define MV_USB_CORE_STATUS_REG(dev) (USB_REG_BASE(dev) + 0x144)
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#define MV_USB_CORE_INTR_REG(dev) (USB_REG_BASE(dev) + 0x148)
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#define MV_USB_CORE_FRAME_INDEX_REG(dev) (USB_REG_BASE(dev) + 0x14C)
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#define MV_USB_CORE_PERIODIC_LIST_BASE_REG(dev) (USB_REG_BASE(dev) + 0x154)
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#define MV_USB_CORE_DEV_ADDR_REG(dev) (USB_REG_BASE(dev) + 0x154)
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#define MV_USB_CORE_ASYNC_LIST_ADDR_REG(dev) (USB_REG_BASE(dev) + 0x158)
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#define MV_USB_CORE_ENDPOINT_LIST_ADDR_REG(dev) (USB_REG_BASE(dev) + 0x158)
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#define MV_USB_CORE_TT_CTRL_REG(dev) (USB_REG_BASE(dev) + 0x15C)
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#define MV_USB_CORE_BURST_SIZE_REG(dev) (USB_REG_BASE(dev) + 0x160)
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#define MV_USB_CORE_TX_FILL_TUNING_REG(dev) (USB_REG_BASE(dev) + 0x164)
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#define MV_USB_CORE_TX_TT_FILL_TUNING_REG(dev) (USB_REG_BASE(dev) + 0x168)
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#define MV_USB_CORE_CONFIG_FLAG_REG(dev) (USB_REG_BASE(dev) + 0x180)
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#define MV_USB_CORE_PORTSC_REG(dev) (USB_REG_BASE(dev) + 0x184)
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#define MV_USB_CORE_OTGSC_REG(dev) (USB_REG_BASE(dev) + 0x1A4)
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#define MV_USB_CORE_MODE_REG(dev) (USB_REG_BASE(dev) + 0x1A8)
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#define MV_USB_CORE_MODE_OFFSET 0
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#define MV_USB_CORE_MODE_MASK (3 << MV_USB_CORE_MODE_OFFSET)
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#define MV_USB_CORE_MODE_HOST (3 << MV_USB_CORE_MODE_OFFSET)
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#define MV_USB_CORE_MODE_DEVICE (2 << MV_USB_CORE_MODE_OFFSET)
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/* Bit[2] (ES) - don't care */
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#define MV_USB_CORE_SETUP_LOCK_DISABLE_BIT 3
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#define MV_USB_CORE_SETUP_LOCK_DISABLE_MASK (1 << MV_USB_CORE_SETUP_LOCK_DISABLE_BIT)
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#define MV_USB_CORE_STREAM_DISABLE_BIT 4
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#define MV_USB_CORE_STREAM_DISABLE_MASK (1 << MV_USB_CORE_STREAM_DISABLE_BIT)
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#define MV_USB_CORE_ENDPT_SETUP_STAT_REG(dev) (USB_REG_BASE(dev) + 0x1AC)
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#define MV_USB_CORE_ENDPT_PRIME_REG(dev) (USB_REG_BASE(dev) + 0x1B0)
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#define MV_USB_CORE_ENDPT_FLUSH_REG(dev) (USB_REG_BASE(dev) + 0x1B4)
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#define MV_USB_CORE_ENDPT_STATUS_REG(dev) (USB_REG_BASE(dev) + 0x1B8)
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#define MV_USB_CORE_ENDPT_COMPLETE_REG(dev) (USB_REG_BASE(dev) + 0x1BC)
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#define MV_USB_CORE_ENDPT_CTRL_REG(dev, ep) (USB_REG_BASE(dev) + 0x1C0 + (ep*4))
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/*******************************************/
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/* Interrupt Controller Registers */
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/*******************************************/
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#define USB_CAUSE_REG(dev) (USB_REG_BASE(dev) + 0x310)
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#define USB_MASK_REG(dev) (USB_REG_BASE(dev) + 0x314)
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#define USB_ERROR_ADDR_REG(dev) (USB_REG_BASE(dev) + 0x31c)
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#define MV_USB_BRIDGE_INTR_CAUSE_REG(dev) (USB_REG_BASE(dev) + 0x310)
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#define MV_USB_BRIDGE_INTR_MASK_REG(dev) (USB_REG_BASE(dev) + 0x314)
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/*******************************************/
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/* USB Bridge Registers */
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/*******************************************/
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/* BITs in Bridge Interrupt Cause and Mask registers */
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#define MV_USB_ADDR_DECODE_ERROR_BIT 0
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#define MV_USB_ADDR_DECODE_ERROR_MASK (1<<MV_USB_ADDR_DECODE_ERROR_BIT)
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#define MV_USB_BRIDGE_ERROR_ADDR_REG(dev) (USB_REG_BASE(dev) + 0x31C)
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#define MV_USB_BRIDGE_CTRL_REG(dev) (USB_REG_BASE(dev) + 0x300)
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#define MV_USB_BRIDGE_CORE_BYTE_SWAP_OFFSET 4
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#define MV_USB_BRIDGE_CORE_BYTE_SWAP_MASK (1 << MV_USB_BRIDGE_CORE_BYTE_SWAP_OFFSET)
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#define MV_USB_BRIDGE_CORE_BYTE_SWAP_EN (0 << MV_USB_BRIDGE_CORE_BYTE_SWAP_OFFSET)
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#define MV_USB_BRIDGE_IPG_REG(dev) (USB_REG_BASE(dev) + 0x360)
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/*******************************************/
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/* USB PHY Registers */
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/*******************************************/
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#define MV_USB_PHY_POWER_CTRL_REG(dev) (USB_REG_BASE(dev) + 0x400)
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#define MV_USB_PHY_POWER_UP_BIT 0
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#define MV_USB_PHY_POWER_UP_MASK (1<<MV_USB_PHY_POWER_UP_BIT)
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#define MV_USB_PHY_PLL_POWER_UP_BIT 1
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#define MV_USB_PHY_PLL_POWER_UP_MASK (1<<MV_USB_PHY_PLL_POWER_UP_BIT)
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#define MV_USB_PHY_PLL_CTRL_REG(dev) (USB_REG_BASE(dev) + 0x410)
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#define MV_USB_PHY_TX_CTRL_REG(dev) (USB_REG_BASE(dev) + 0x420)
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#define MV_USB_PHY_RX_CTRL_REG(dev) (USB_REG_BASE(dev) + 0x430)
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#define MV_USB_PHY_IVREF_CTRL_REG(dev) (USB_REG_BASE(dev) + 0x440)
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#define MV_USB_PHY_TEST_GROUP_CTRL_REG_0(dev) (USB_REG_BASE(dev) + 0x450)
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#define MV_USB_PHY_TEST_GROUP_CTRL_REG_1(dev) (USB_REG_BASE(dev) + 0x454)
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* __INCmvUsbRegsh */
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