463 lines
17 KiB
C
463 lines
17 KiB
C
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/******************************************************************************
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*
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* Author: Xilinx, Inc.
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
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* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
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* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
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* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
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* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
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* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
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* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
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* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
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* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
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* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
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* FITNESS FOR A PARTICULAR PURPOSE.
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*
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*
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* Xilinx hardware products are not intended for use in life support
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* appliances, devices, or systems. Use in such applications is
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* expressly prohibited.
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*
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*
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* (c) Copyright 2002-2004 Xilinx Inc.
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* All rights reserved.
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*
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xemac_l.h
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*
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* This header file contains identifiers and low-level driver functions (or
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* macros) that can be used to access the device. High-level driver functions
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* are defined in xemac.h.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -----------------------------------------------
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* 1.00b rpm 04/26/02 First release
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* 1.00b rmm 09/23/02 Added XEmac_mPhyReset macro
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* 1.00c rpm 12/05/02 New version includes support for simple DMA
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* </pre>
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*
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******************************************************************************/
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#ifndef XEMAC_L_H /* prevent circular inclusions */
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#define XEMAC_L_H /* by using protection macros */
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/***************************** Include Files *********************************/
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#include "xbasic_types.h"
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#include "xio.h"
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/************************** Constant Definitions *****************************/
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/* Offset of the MAC registers from the IPIF base address */
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#define XEM_REG_OFFSET 0x1100UL
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/*
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* Register offsets for the Ethernet MAC. Each register is 32 bits.
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*/
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#define XEM_EMIR_OFFSET (XEM_REG_OFFSET + 0x0) /* EMAC Module ID */
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#define XEM_ECR_OFFSET (XEM_REG_OFFSET + 0x4) /* MAC Control */
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#define XEM_IFGP_OFFSET (XEM_REG_OFFSET + 0x8) /* Interframe Gap */
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#define XEM_SAH_OFFSET (XEM_REG_OFFSET + 0xC) /* Station addr, high */
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#define XEM_SAL_OFFSET (XEM_REG_OFFSET + 0x10) /* Station addr, low */
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#define XEM_MGTCR_OFFSET (XEM_REG_OFFSET + 0x14) /* MII mgmt control */
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#define XEM_MGTDR_OFFSET (XEM_REG_OFFSET + 0x18) /* MII mgmt data */
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#define XEM_RPLR_OFFSET (XEM_REG_OFFSET + 0x1C) /* Rx packet length */
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#define XEM_TPLR_OFFSET (XEM_REG_OFFSET + 0x20) /* Tx packet length */
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#define XEM_TSR_OFFSET (XEM_REG_OFFSET + 0x24) /* Tx status */
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#define XEM_RMFC_OFFSET (XEM_REG_OFFSET + 0x28) /* Rx missed frames */
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#define XEM_RCC_OFFSET (XEM_REG_OFFSET + 0x2C) /* Rx collisions */
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#define XEM_RFCSEC_OFFSET (XEM_REG_OFFSET + 0x30) /* Rx FCS errors */
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#define XEM_RAEC_OFFSET (XEM_REG_OFFSET + 0x34) /* Rx alignment errors */
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#define XEM_TEDC_OFFSET (XEM_REG_OFFSET + 0x38) /* Transmit excess
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* deferral cnt */
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/*
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* Register offsets for the IPIF components
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*/
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#define XEM_ISR_OFFSET 0x20UL /* Interrupt status */
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#define XEM_DMA_OFFSET 0x2300UL
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#define XEM_DMA_SEND_OFFSET (XEM_DMA_OFFSET + 0x0) /* DMA send channel */
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#define XEM_DMA_RECV_OFFSET (XEM_DMA_OFFSET + 0x40) /* DMA recv channel */
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#define XEM_PFIFO_OFFSET 0x2000UL
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#define XEM_PFIFO_TXREG_OFFSET (XEM_PFIFO_OFFSET + 0x0) /* Tx registers */
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#define XEM_PFIFO_RXREG_OFFSET (XEM_PFIFO_OFFSET + 0x10) /* Rx registers */
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#define XEM_PFIFO_TXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x100) /* Tx keyhole */
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#define XEM_PFIFO_RXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x200) /* Rx keyhole */
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/*
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* EMAC Module Identification Register (EMIR)
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*/
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#define XEM_EMIR_VERSION_MASK 0xFFFF0000UL /* Device version */
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#define XEM_EMIR_TYPE_MASK 0x0000FF00UL /* Device type */
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/*
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* EMAC Control Register (ECR)
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*/
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#define XEM_ECR_FULL_DUPLEX_MASK 0x80000000UL /* Full duplex mode */
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#define XEM_ECR_XMIT_RESET_MASK 0x40000000UL /* Reset transmitter */
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#define XEM_ECR_XMIT_ENABLE_MASK 0x20000000UL /* Enable transmitter */
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#define XEM_ECR_RECV_RESET_MASK 0x10000000UL /* Reset receiver */
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#define XEM_ECR_RECV_ENABLE_MASK 0x08000000UL /* Enable receiver */
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#define XEM_ECR_PHY_ENABLE_MASK 0x04000000UL /* Enable PHY */
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#define XEM_ECR_XMIT_PAD_ENABLE_MASK 0x02000000UL /* Enable xmit pad insert */
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#define XEM_ECR_XMIT_FCS_ENABLE_MASK 0x01000000UL /* Enable xmit FCS insert */
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#define XEM_ECR_XMIT_ADDR_INSERT_MASK 0x00800000UL /* Enable xmit source addr
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* insertion */
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#define XEM_ECR_XMIT_ERROR_INSERT_MASK 0x00400000UL /* Insert xmit error */
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#define XEM_ECR_XMIT_ADDR_OVWRT_MASK 0x00200000UL /* Enable xmit source addr
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* overwrite */
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#define XEM_ECR_LOOPBACK_MASK 0x00100000UL /* Enable internal
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* loopback */
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#define XEM_ECR_RECV_STRIP_ENABLE_MASK 0x00080000UL /* Enable recv pad/fcs strip */
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#define XEM_ECR_UNICAST_ENABLE_MASK 0x00020000UL /* Enable unicast addr */
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#define XEM_ECR_MULTI_ENABLE_MASK 0x00010000UL /* Enable multicast addr */
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#define XEM_ECR_BROAD_ENABLE_MASK 0x00008000UL /* Enable broadcast addr */
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#define XEM_ECR_PROMISC_ENABLE_MASK 0x00004000UL /* Enable promiscuous mode */
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#define XEM_ECR_RECV_ALL_MASK 0x00002000UL /* Receive all frames */
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#define XEM_ECR_RESERVED2_MASK 0x00001000UL /* Reserved */
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#define XEM_ECR_MULTI_HASH_ENABLE_MASK 0x00000800UL /* Enable multicast hash */
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#define XEM_ECR_PAUSE_FRAME_MASK 0x00000400UL /* Interpret pause frames */
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#define XEM_ECR_CLEAR_HASH_MASK 0x00000200UL /* Clear hash table */
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#define XEM_ECR_ADD_HASH_ADDR_MASK 0x00000100UL /* Add hash table address */
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/*
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* Interframe Gap Register (IFGR)
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*/
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#define XEM_IFGP_PART1_MASK 0xF8000000UL /* Interframe Gap Part1 */
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#define XEM_IFGP_PART1_SHIFT 27
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#define XEM_IFGP_PART2_MASK 0x07C00000UL /* Interframe Gap Part2 */
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#define XEM_IFGP_PART2_SHIFT 22
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/*
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* Station Address High Register (SAH)
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*/
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#define XEM_SAH_ADDR_MASK 0x0000FFFFUL /* Station address high bytes */
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/*
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* Station Address Low Register (SAL)
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*/
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#define XEM_SAL_ADDR_MASK 0xFFFFFFFFUL /* Station address low bytes */
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/*
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* MII Management Control Register (MGTCR)
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*/
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#define XEM_MGTCR_START_MASK 0x80000000UL /* Start/Busy */
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#define XEM_MGTCR_RW_NOT_MASK 0x40000000UL /* Read/Write Not (direction) */
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#define XEM_MGTCR_PHY_ADDR_MASK 0x3E000000UL /* PHY address */
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#define XEM_MGTCR_PHY_ADDR_SHIFT 25 /* PHY address shift */
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#define XEM_MGTCR_REG_ADDR_MASK 0x01F00000UL /* Register address */
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#define XEM_MGTCR_REG_ADDR_SHIFT 20 /* Register addr shift */
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#define XEM_MGTCR_MII_ENABLE_MASK 0x00080000UL /* Enable MII from EMAC */
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#define XEM_MGTCR_RD_ERROR_MASK 0x00040000UL /* MII mgmt read error */
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/*
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* MII Management Data Register (MGTDR)
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*/
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#define XEM_MGTDR_DATA_MASK 0x0000FFFFUL /* MII data */
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/*
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* Receive Packet Length Register (RPLR)
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*/
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#define XEM_RPLR_LENGTH_MASK 0x0000FFFFUL /* Receive packet length */
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/*
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* Transmit Packet Length Register (TPLR)
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*/
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#define XEM_TPLR_LENGTH_MASK 0x0000FFFFUL /* Transmit packet length */
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/*
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* Transmit Status Register (TSR)
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*/
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#define XEM_TSR_EXCESS_DEFERRAL_MASK 0x80000000UL /* Transmit excess deferral */
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#define XEM_TSR_FIFO_UNDERRUN_MASK 0x40000000UL /* Packet FIFO underrun */
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#define XEM_TSR_ATTEMPTS_MASK 0x3E000000UL /* Transmission attempts */
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#define XEM_TSR_LATE_COLLISION_MASK 0x01000000UL /* Transmit late collision */
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/*
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* Receive Missed Frame Count (RMFC)
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*/
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#define XEM_RMFC_DATA_MASK 0x0000FFFFUL
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/*
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* Receive Collision Count (RCC)
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*/
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#define XEM_RCC_DATA_MASK 0x0000FFFFUL
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/*
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* Receive FCS Error Count (RFCSEC)
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*/
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#define XEM_RFCSEC_DATA_MASK 0x0000FFFFUL
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/*
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* Receive Alignment Error Count (RALN)
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*/
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#define XEM_RAEC_DATA_MASK 0x0000FFFFUL
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/*
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* Transmit Excess Deferral Count (TEDC)
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*/
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#define XEM_TEDC_DATA_MASK 0x0000FFFFUL
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/*
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* EMAC Interrupt Registers (Status and Enable) masks. These registers are
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* part of the IPIF IP Interrupt registers
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*/
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#define XEM_EIR_XMIT_DONE_MASK 0x00000001UL /* Xmit complete */
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#define XEM_EIR_RECV_DONE_MASK 0x00000002UL /* Recv complete */
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#define XEM_EIR_XMIT_ERROR_MASK 0x00000004UL /* Xmit error */
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#define XEM_EIR_RECV_ERROR_MASK 0x00000008UL /* Recv error */
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#define XEM_EIR_XMIT_SFIFO_EMPTY_MASK 0x00000010UL /* Xmit status fifo empty */
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#define XEM_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020UL /* Recv length fifo empty */
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#define XEM_EIR_XMIT_LFIFO_FULL_MASK 0x00000040UL /* Xmit length fifo full */
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#define XEM_EIR_RECV_LFIFO_OVER_MASK 0x00000080UL /* Recv length fifo
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* overrun */
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#define XEM_EIR_RECV_LFIFO_UNDER_MASK 0x00000100UL /* Recv length fifo
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* underrun */
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#define XEM_EIR_XMIT_SFIFO_OVER_MASK 0x00000200UL /* Xmit status fifo
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* overrun */
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#define XEM_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400UL /* Transmit status fifo
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* underrun */
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#define XEM_EIR_XMIT_LFIFO_OVER_MASK 0x00000800UL /* Transmit length fifo
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* overrun */
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#define XEM_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000UL /* Transmit length fifo
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* underrun */
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#define XEM_EIR_XMIT_PAUSE_MASK 0x00002000UL /* Transmit pause pkt
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* received */
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#define XEM_EIR_RECV_DFIFO_OVER_MASK 0x00004000UL /* Receive data fifo
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* overrun */
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#define XEM_EIR_RECV_MISSED_FRAME_MASK 0x00008000UL /* Receive missed frame
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* error */
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#define XEM_EIR_RECV_COLLISION_MASK 0x00010000UL /* Receive collision
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* error */
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#define XEM_EIR_RECV_FCS_ERROR_MASK 0x00020000UL /* Receive FCS error */
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#define XEM_EIR_RECV_LEN_ERROR_MASK 0x00040000UL /* Receive length field
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* error */
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#define XEM_EIR_RECV_SHORT_ERROR_MASK 0x00080000UL /* Receive short frame
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* error */
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#define XEM_EIR_RECV_LONG_ERROR_MASK 0x00100000UL /* Receive long frame
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* error */
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#define XEM_EIR_RECV_ALIGN_ERROR_MASK 0x00200000UL /* Receive alignment
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* error */
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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/*****************************************************************************
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*
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* Low-level driver macros and functions. The list below provides signatures
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* to help the user use the macros.
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*
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* u32 XEmac_mReadReg(u32 BaseAddress, int RegOffset)
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* void XEmac_mWriteReg(u32 BaseAddress, int RegOffset, u32 Mask)
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*
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* void XEmac_mSetControlReg(u32 BaseAddress, u32 Mask)
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* void XEmac_mSetMacAddress(u32 BaseAddress, u8 *AddressPtr)
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*
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* void XEmac_mEnable(u32 BaseAddress)
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* void XEmac_mDisable(u32 BaseAddress)
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*
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* u32 XEmac_mIsTxDone(u32 BaseAddress)
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* u32 XEmac_mIsRxEmpty(u32 BaseAddress)
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*
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* void XEmac_SendFrame(u32 BaseAddress, u8 *FramePtr, int Size)
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* int XEmac_RecvFrame(u32 BaseAddress, u8 *FramePtr)
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*
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*****************************************************************************/
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/****************************************************************************/
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/**
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*
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* Read the given register.
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*
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* @param BaseAddress is the base address of the device
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* @param RegOffset is the register offset to be read
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*
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* @return The 32-bit value of the register
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*
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* @note None.
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*
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*****************************************************************************/
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#define XEmac_mReadReg(BaseAddress, RegOffset) \
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XIo_In32((BaseAddress) + (RegOffset))
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/****************************************************************************/
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/**
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*
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* Write the given register.
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*
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* @param BaseAddress is the base address of the device
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* @param RegOffset is the register offset to be written
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* @param Data is the 32-bit value to write to the register
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*
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* @return None.
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*
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* @note None.
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*
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*****************************************************************************/
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#define XEmac_mWriteReg(BaseAddress, RegOffset, Data) \
|
||
|
|
XIo_Out32((BaseAddress) + (RegOffset), (Data))
|
||
|
|
|
||
|
|
/****************************************************************************/
|
||
|
|
/**
|
||
|
|
*
|
||
|
|
* Set the contents of the control register. Use the XEM_ECR_* constants
|
||
|
|
* defined above to create the bit-mask to be written to the register.
|
||
|
|
*
|
||
|
|
* @param BaseAddress is the base address of the device
|
||
|
|
* @param Mask is the 16-bit value to write to the control register
|
||
|
|
*
|
||
|
|
* @return None.
|
||
|
|
*
|
||
|
|
* @note None.
|
||
|
|
*
|
||
|
|
*****************************************************************************/
|
||
|
|
#define XEmac_mSetControlReg(BaseAddress, Mask) \
|
||
|
|
XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, (Mask))
|
||
|
|
|
||
|
|
/****************************************************************************/
|
||
|
|
/**
|
||
|
|
*
|
||
|
|
* Set the station address of the EMAC device.
|
||
|
|
*
|
||
|
|
* @param BaseAddress is the base address of the device
|
||
|
|
* @param AddressPtr is a pointer to a 6-byte MAC address
|
||
|
|
*
|
||
|
|
* @return None.
|
||
|
|
*
|
||
|
|
* @note None.
|
||
|
|
*
|
||
|
|
*****************************************************************************/
|
||
|
|
#define XEmac_mSetMacAddress(BaseAddress, AddressPtr) \
|
||
|
|
{ \
|
||
|
|
u32 MacAddr; \
|
||
|
|
\
|
||
|
|
MacAddr = ((AddressPtr)[0] << 8) | (AddressPtr)[1]; \
|
||
|
|
XIo_Out32((BaseAddress) + XEM_SAH_OFFSET, MacAddr); \
|
||
|
|
\
|
||
|
|
MacAddr = ((AddressPtr)[2] << 24) | ((AddressPtr)[3] << 16) | \
|
||
|
|
((AddressPtr)[4] << 8) | (AddressPtr)[5]; \
|
||
|
|
\
|
||
|
|
XIo_Out32((BaseAddress) + XEM_SAL_OFFSET, MacAddr); \
|
||
|
|
}
|
||
|
|
|
||
|
|
/****************************************************************************/
|
||
|
|
/**
|
||
|
|
*
|
||
|
|
* Enable the transmitter and receiver. Preserve the contents of the control
|
||
|
|
* register.
|
||
|
|
*
|
||
|
|
* @param BaseAddress is the base address of the device
|
||
|
|
*
|
||
|
|
* @return None.
|
||
|
|
*
|
||
|
|
* @note None.
|
||
|
|
*
|
||
|
|
*****************************************************************************/
|
||
|
|
#define XEmac_mEnable(BaseAddress) \
|
||
|
|
{ \
|
||
|
|
u32 Control; \
|
||
|
|
Control = XIo_In32((BaseAddress) + XEM_ECR_OFFSET); \
|
||
|
|
Control &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK); \
|
||
|
|
Control |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK); \
|
||
|
|
XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, Control); \
|
||
|
|
}
|
||
|
|
|
||
|
|
/****************************************************************************/
|
||
|
|
/**
|
||
|
|
*
|
||
|
|
* Disable the transmitter and receiver. Preserve the contents of the control
|
||
|
|
* register.
|
||
|
|
*
|
||
|
|
* @param BaseAddress is the base address of the device
|
||
|
|
*
|
||
|
|
* @return None.
|
||
|
|
*
|
||
|
|
* @note None.
|
||
|
|
*
|
||
|
|
*****************************************************************************/
|
||
|
|
#define XEmac_mDisable(BaseAddress) \
|
||
|
|
XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, \
|
||
|
|
XIo_In32((BaseAddress) + XEM_ECR_OFFSET) & \
|
||
|
|
~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK))
|
||
|
|
|
||
|
|
/****************************************************************************/
|
||
|
|
/**
|
||
|
|
*
|
||
|
|
* Check to see if the transmission is complete.
|
||
|
|
*
|
||
|
|
* @param BaseAddress is the base address of the device
|
||
|
|
*
|
||
|
|
* @return TRUE if it is done, or FALSE if it is not.
|
||
|
|
*
|
||
|
|
* @note None.
|
||
|
|
*
|
||
|
|
*****************************************************************************/
|
||
|
|
#define XEmac_mIsTxDone(BaseAddress) \
|
||
|
|
(XIo_In32((BaseAddress) + XEM_ISR_OFFSET) & XEM_EIR_XMIT_DONE_MASK)
|
||
|
|
|
||
|
|
/****************************************************************************/
|
||
|
|
/**
|
||
|
|
*
|
||
|
|
* Check to see if the receive FIFO is empty.
|
||
|
|
*
|
||
|
|
* @param BaseAddress is the base address of the device
|
||
|
|
*
|
||
|
|
* @return TRUE if it is empty, or FALSE if it is not.
|
||
|
|
*
|
||
|
|
* @note None.
|
||
|
|
*
|
||
|
|
*****************************************************************************/
|
||
|
|
#define XEmac_mIsRxEmpty(BaseAddress) \
|
||
|
|
(!(XIo_In32((BaseAddress) + XEM_ISR_OFFSET) & XEM_EIR_RECV_DONE_MASK))
|
||
|
|
|
||
|
|
/****************************************************************************/
|
||
|
|
/**
|
||
|
|
*
|
||
|
|
* Reset MII compliant PHY
|
||
|
|
*
|
||
|
|
* @param BaseAddress is the base address of the device
|
||
|
|
*
|
||
|
|
* @return None.
|
||
|
|
*
|
||
|
|
* @note None.
|
||
|
|
*
|
||
|
|
*****************************************************************************/
|
||
|
|
#define XEmac_mPhyReset(BaseAddress) \
|
||
|
|
{ \
|
||
|
|
u32 Control; \
|
||
|
|
Control = XIo_In32((BaseAddress) + XEM_ECR_OFFSET); \
|
||
|
|
Control &= ~XEM_ECR_PHY_ENABLE_MASK; \
|
||
|
|
XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, Control); \
|
||
|
|
Control |= XEM_ECR_PHY_ENABLE_MASK; \
|
||
|
|
XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, Control); \
|
||
|
|
}
|
||
|
|
|
||
|
|
/************************** Function Prototypes ******************************/
|
||
|
|
|
||
|
|
void XEmac_SendFrame(u32 BaseAddress, u8 * FramePtr, int Size);
|
||
|
|
int XEmac_RecvFrame(u32 BaseAddress, u8 * FramePtr);
|
||
|
|
|
||
|
|
#endif /* end of protection macro */
|