367 lines
9.2 KiB
C
367 lines
9.2 KiB
C
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/*
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* (C) Copyright 2003
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* Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
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*
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* (C) Copyright 2002
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* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h> /* core U-Boot definitions */
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#include <ACEX1K.h> /* ACEX device family */
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#if (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K))
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/* Define FPGA_DEBUG to get debug printf's */
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#ifdef FPGA_DEBUG
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#define PRINTF(fmt,args...) printf (fmt ,##args)
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#else
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#define PRINTF(fmt,args...)
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#endif
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/* Note: The assumption is that we cannot possibly run fast enough to
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* overrun the device (the Slave Parallel mode can free run at 50MHz).
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* If there is a need to operate slower, define CONFIG_FPGA_DELAY in
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* the board config file to slow things down.
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*/
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#ifndef CONFIG_FPGA_DELAY
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#define CONFIG_FPGA_DELAY()
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#endif
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#ifndef CFG_FPGA_WAIT
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#define CFG_FPGA_WAIT CFG_HZ/10 /* 100 ms */
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#endif
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static int ACEX1K_ps_load( Altera_desc *desc, void *buf, size_t bsize );
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static int ACEX1K_ps_dump( Altera_desc *desc, void *buf, size_t bsize );
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/* static int ACEX1K_ps_info( Altera_desc *desc ); */
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static int ACEX1K_ps_reloc( Altera_desc *desc, ulong reloc_offset );
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/* ------------------------------------------------------------------------- */
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/* ACEX1K Generic Implementation */
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int ACEX1K_load (Altera_desc * desc, void *buf, size_t bsize)
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{
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int ret_val = FPGA_FAIL;
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switch (desc->iface) {
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case passive_serial:
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PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__);
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ret_val = ACEX1K_ps_load (desc, buf, bsize);
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break;
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/* Add new interface types here */
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default:
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printf ("%s: Unsupported interface type, %d\n",
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__FUNCTION__, desc->iface);
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}
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return ret_val;
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}
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int ACEX1K_dump (Altera_desc * desc, void *buf, size_t bsize)
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{
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int ret_val = FPGA_FAIL;
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switch (desc->iface) {
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case passive_serial:
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PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__);
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ret_val = ACEX1K_ps_dump (desc, buf, bsize);
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break;
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/* Add new interface types here */
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default:
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printf ("%s: Unsupported interface type, %d\n",
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__FUNCTION__, desc->iface);
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}
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return ret_val;
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}
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int ACEX1K_info( Altera_desc *desc )
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{
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return FPGA_SUCCESS;
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}
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int ACEX1K_reloc (Altera_desc * desc, ulong reloc_offset)
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{
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int ret_val = FPGA_FAIL; /* assume a failure */
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if (desc->family != Altera_ACEX1K) {
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printf ("%s: Unsupported family type, %d\n",
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__FUNCTION__, desc->family);
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return FPGA_FAIL;
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} else
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switch (desc->iface) {
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case passive_serial:
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ret_val = ACEX1K_ps_reloc (desc, reloc_offset);
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break;
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/* Add new interface types here */
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default:
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printf ("%s: Unsupported interface type, %d\n",
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__FUNCTION__, desc->iface);
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}
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return ret_val;
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}
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/* ------------------------------------------------------------------------- */
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/* ACEX1K Passive Serial Generic Implementation */
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static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize)
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{
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int ret_val = FPGA_FAIL; /* assume the worst */
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Altera_ACEX1K_Passive_Serial_fns *fn = desc->iface_fns;
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int i;
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PRINTF ("%s: start with interface functions @ 0x%p\n",
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__FUNCTION__, fn);
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if (fn) {
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size_t bytecount = 0;
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unsigned char *data = (unsigned char *) buf;
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int cookie = desc->cookie; /* make a local copy */
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unsigned long ts; /* timestamp */
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PRINTF ("%s: Function Table:\n"
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"ptr:\t0x%p\n"
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"struct: 0x%p\n"
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"config:\t0x%p\n"
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"status:\t0x%p\n"
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"clk:\t0x%p\n"
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"data:\t0x%p\n"
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"done:\t0x%p\n\n",
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__FUNCTION__, &fn, fn, fn->config, fn->status,
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fn->clk, fn->data, fn->done);
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#ifdef CFG_FPGA_PROG_FEEDBACK
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printf ("Loading FPGA Device %d...", cookie);
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#endif
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/*
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* Run the pre configuration function if there is one.
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*/
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if (*fn->pre) {
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(*fn->pre) (cookie);
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}
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/* Establish the initial state */
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(*fn->config) (TRUE, TRUE, cookie); /* Assert nCONFIG */
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udelay(2); /* T_cfg > 2us */
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/* nSTATUS should be asserted now */
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(*fn->done) (cookie);
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if ( !(*fn->status) (cookie) ) {
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puts ("** nSTATUS is not asserted.\n");
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(*fn->abort) (cookie);
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return FPGA_FAIL;
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}
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(*fn->config) (FALSE, TRUE, cookie); /* Deassert nCONFIG */
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udelay(2); /* T_cf2st1 < 4us */
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/* Wait for nSTATUS to be released (i.e. deasserted) */
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ts = get_timer (0); /* get current time */
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do {
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CONFIG_FPGA_DELAY ();
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if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
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puts ("** Timeout waiting for STATUS to go high.\n");
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(*fn->abort) (cookie);
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return FPGA_FAIL;
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}
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(*fn->done) (cookie);
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} while ((*fn->status) (cookie));
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/* Get ready for the burn */
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CONFIG_FPGA_DELAY ();
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/* Load the data */
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while (bytecount < bsize) {
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unsigned char val=0;
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#ifdef CFG_FPGA_CHECK_CTRLC
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if (ctrlc ()) {
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(*fn->abort) (cookie);
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return FPGA_FAIL;
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}
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#endif
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/* Altera detects an error if INIT goes low (active)
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while DONE is low (inactive) */
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#if 0 /* not yet implemented */
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if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
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puts ("** CRC error during FPGA load.\n");
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(*fn->abort) (cookie);
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return (FPGA_FAIL);
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}
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#endif
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val = data [bytecount ++ ];
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i = 8;
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do {
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/* Deassert the clock */
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(*fn->clk) (FALSE, TRUE, cookie);
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CONFIG_FPGA_DELAY ();
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/* Write data */
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(*fn->data) ( (val & 0x01), TRUE, cookie);
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CONFIG_FPGA_DELAY ();
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/* Assert the clock */
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(*fn->clk) (TRUE, TRUE, cookie);
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CONFIG_FPGA_DELAY ();
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val >>= 1;
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i --;
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} while (i > 0);
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#ifdef CFG_FPGA_PROG_FEEDBACK
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if (bytecount % (bsize / 40) == 0)
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putc ('.'); /* let them know we are alive */
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#endif
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}
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CONFIG_FPGA_DELAY ();
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#ifdef CFG_FPGA_PROG_FEEDBACK
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putc (' '); /* terminate the dotted line */
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#endif
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/*
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* Checking FPGA's CONF_DONE signal - correctly booted ?
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*/
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if ( ! (*fn->done) (cookie) ) {
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puts ("** Booting failed! CONF_DONE is still deasserted.\n");
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(*fn->abort) (cookie);
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return (FPGA_FAIL);
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}
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/*
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* "DCLK must be clocked an additional 10 times fpr ACEX 1K..."
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*/
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for (i = 0; i < 12; i++) {
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CONFIG_FPGA_DELAY ();
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(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
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CONFIG_FPGA_DELAY ();
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(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
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}
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ret_val = FPGA_SUCCESS;
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#ifdef CFG_FPGA_PROG_FEEDBACK
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if (ret_val == FPGA_SUCCESS) {
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puts ("Done.\n");
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}
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else {
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puts ("Fail.\n");
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}
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#endif
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(*fn->post) (cookie);
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} else {
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printf ("%s: NULL Interface function table!\n", __FUNCTION__);
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}
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return ret_val;
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}
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static int ACEX1K_ps_dump (Altera_desc * desc, void *buf, size_t bsize)
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{
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/* Readback is only available through the Slave Parallel and */
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/* boundary-scan interfaces. */
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printf ("%s: Passive Serial Dumping is unavailable\n",
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__FUNCTION__);
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return FPGA_FAIL;
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}
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static int ACEX1K_ps_reloc (Altera_desc * desc, ulong reloc_offset)
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{
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int ret_val = FPGA_FAIL; /* assume the worst */
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Altera_ACEX1K_Passive_Serial_fns *fn_r, *fn =
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(Altera_ACEX1K_Passive_Serial_fns *) (desc->iface_fns);
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if (fn) {
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ulong addr;
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/* Get the relocated table address */
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addr = (ulong) fn + reloc_offset;
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fn_r = (Altera_ACEX1K_Passive_Serial_fns *) addr;
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if (!fn_r->relocated) {
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if (memcmp (fn_r, fn,
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sizeof (Altera_ACEX1K_Passive_Serial_fns))
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== 0) {
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/* good copy of the table, fix the descriptor pointer */
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desc->iface_fns = fn_r;
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} else {
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PRINTF ("%s: Invalid function table at 0x%p\n",
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__FUNCTION__, fn_r);
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return FPGA_FAIL;
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}
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PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
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desc);
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addr = (ulong) (fn->pre) + reloc_offset;
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fn_r->pre = (Altera_pre_fn) addr;
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addr = (ulong) (fn->config) + reloc_offset;
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fn_r->config = (Altera_config_fn) addr;
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addr = (ulong) (fn->status) + reloc_offset;
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fn_r->status = (Altera_status_fn) addr;
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addr = (ulong) (fn->done) + reloc_offset;
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fn_r->done = (Altera_done_fn) addr;
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addr = (ulong) (fn->clk) + reloc_offset;
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fn_r->clk = (Altera_clk_fn) addr;
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addr = (ulong) (fn->data) + reloc_offset;
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fn_r->data = (Altera_data_fn) addr;
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addr = (ulong) (fn->abort) + reloc_offset;
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fn_r->abort = (Altera_abort_fn) addr;
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addr = (ulong) (fn->post) + reloc_offset;
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fn_r->post = (Altera_post_fn) addr;
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fn_r->relocated = TRUE;
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} else {
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/* this table has already been moved */
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/* XXX - should check to see if the descriptor is correct */
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desc->iface_fns = fn_r;
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}
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ret_val = FPGA_SUCCESS;
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} else {
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printf ("%s: NULL Interface function table!\n", __FUNCTION__);
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}
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return ret_val;
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}
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#endif /* (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K)) */
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