558 lines
15 KiB
C
558 lines
15 KiB
C
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/*
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* (C) Copyright 2002
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* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
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* Keith Outwater, keith_outwater@mvis.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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/*
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* Configuration support for Xilinx Virtex2 devices. Based
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* on spartan2.c (Rich Ireland, rireland@enterasys.com).
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*/
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#include <common.h>
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#include <virtex2.h>
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#if (CONFIG_FPGA & (CFG_XILINX | CFG_VIRTEX2))
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#if 0
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#define FPGA_DEBUG
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#endif
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#ifdef FPGA_DEBUG
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#define PRINTF(fmt,args...) printf (fmt ,##args)
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#else
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#define PRINTF(fmt,args...)
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#endif
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/*
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* If the SelectMap interface can be overrun by the processor, define
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* CFG_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board configuration
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* file and add board-specific support for checking BUSY status. By default,
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* assume that the SelectMap interface cannot be overrun.
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*/
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#ifndef CFG_FPGA_CHECK_BUSY
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#undef CFG_FPGA_CHECK_BUSY
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#endif
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#ifndef CONFIG_FPGA_DELAY
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#define CONFIG_FPGA_DELAY()
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#endif
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#ifndef CFG_FPGA_PROG_FEEDBACK
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#define CFG_FPGA_PROG_FEEDBACK
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#endif
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/*
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* Don't allow config cycle to be interrupted
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*/
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#ifndef CFG_FPGA_CHECK_CTRLC
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#undef CFG_FPGA_CHECK_CTRLC
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#endif
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/*
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* Check for errors during configuration by default
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*/
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#ifndef CFG_FPGA_CHECK_ERROR
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#define CFG_FPGA_CHECK_ERROR
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#endif
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/*
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* The default timeout in mS for INIT_B to deassert after PROG_B has
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* been deasserted. Per the latest Virtex II Handbook (page 347), the
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* max time from PORG_B deassertion to INIT_B deassertion is 4uS per
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* data frame for the XC2V8000. The XC2V8000 has 2860 data frames
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* which yields 11.44 mS. So let's make it bigger in order to handle
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* an XC2V1000, if anyone can ever get ahold of one.
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*/
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#ifndef CFG_FPGA_WAIT_INIT
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#define CFG_FPGA_WAIT_INIT CFG_HZ/2 /* 500 ms */
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#endif
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/*
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* The default timeout for waiting for BUSY to deassert during configuration.
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* This is normally not necessary since for most reasonable configuration
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* clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary.
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*/
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#ifndef CFG_FPGA_WAIT_BUSY
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#define CFG_FPGA_WAIT_BUSY CFG_HZ/200 /* 5 ms*/
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#endif
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/* Default timeout for waiting for FPGA to enter operational mode after
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* configuration data has been written.
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*/
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#ifndef CFG_FPGA_WAIT_CONFIG
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#define CFG_FPGA_WAIT_CONFIG CFG_HZ/5 /* 200 ms */
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#endif
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static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize);
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static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize);
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static int Virtex2_ssm_reloc (Xilinx_desc * desc, ulong reloc_offset);
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static int Virtex2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize);
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static int Virtex2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize);
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static int Virtex2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset);
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int Virtex2_load (Xilinx_desc * desc, void *buf, size_t bsize)
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{
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int ret_val = FPGA_FAIL;
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switch (desc->iface) {
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case slave_serial:
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PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
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ret_val = Virtex2_ss_load (desc, buf, bsize);
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break;
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case slave_selectmap:
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PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
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ret_val = Virtex2_ssm_load (desc, buf, bsize);
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break;
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default:
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printf ("%s: Unsupported interface type, %d\n",
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__FUNCTION__, desc->iface);
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}
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return ret_val;
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}
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int Virtex2_dump (Xilinx_desc * desc, void *buf, size_t bsize)
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{
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int ret_val = FPGA_FAIL;
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switch (desc->iface) {
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case slave_serial:
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PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
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ret_val = Virtex2_ss_dump (desc, buf, bsize);
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break;
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case slave_parallel:
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PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
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ret_val = Virtex2_ssm_dump (desc, buf, bsize);
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break;
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default:
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printf ("%s: Unsupported interface type, %d\n",
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__FUNCTION__, desc->iface);
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}
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return ret_val;
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}
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int Virtex2_info (Xilinx_desc * desc)
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{
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return FPGA_SUCCESS;
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}
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int Virtex2_reloc (Xilinx_desc * desc, ulong reloc_offset)
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{
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int ret_val = FPGA_FAIL;
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if (desc->family != Xilinx_Virtex2) {
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printf ("%s: Unsupported family type, %d\n",
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__FUNCTION__, desc->family);
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return FPGA_FAIL;
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} else
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switch (desc->iface) {
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case slave_serial:
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ret_val = Virtex2_ss_reloc (desc, reloc_offset);
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break;
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case slave_selectmap:
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ret_val = Virtex2_ssm_reloc (desc, reloc_offset);
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break;
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default:
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printf ("%s: Unsupported interface type, %d\n",
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__FUNCTION__, desc->iface);
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}
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return ret_val;
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}
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/*
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* Virtex-II Slave SelectMap configuration loader. Configuration via
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* SelectMap is as follows:
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* 1. Set the FPGA's PROG_B line low.
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* 2. Set the FPGA's PROG_B line high. Wait for INIT_B to go high.
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* 3. Write data to the SelectMap port. If INIT_B goes low at any time
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* this process, a configuration error (most likely CRC failure) has
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* ocurred. At this point a status word may be read from the
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* SelectMap interface to determine the source of the problem (You
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* could, for instance, put this in your 'abort' function handler).
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* 4. After all data has been written, test the state of the FPGA
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* INIT_B and DONE lines. If both are high, configuration has
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* succeeded. Congratulations!
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*/
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static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize)
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{
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int ret_val = FPGA_FAIL;
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Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns;
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PRINTF ("%s:%d: Start with interface functions @ 0x%p\n",
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__FUNCTION__, __LINE__, fn);
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if (fn) {
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size_t bytecount = 0;
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unsigned char *data = (unsigned char *) buf;
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int cookie = desc->cookie;
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unsigned long ts;
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/* Gotta split this one up (so the stack won't blow??) */
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PRINTF ("%s:%d: Function Table:\n"
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" base 0x%p\n"
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" struct 0x%p\n"
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" pre 0x%p\n"
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" prog 0x%p\n"
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" init 0x%p\n"
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" error 0x%p\n",
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__FUNCTION__, __LINE__,
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&fn, fn, fn->pre, fn->pgm, fn->init, fn->err);
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PRINTF (" clock 0x%p\n"
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" cs 0x%p\n"
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" write 0x%p\n"
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" rdata 0x%p\n"
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" wdata 0x%p\n"
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" busy 0x%p\n"
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" abort 0x%p\n"
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" post 0x%p\n\n",
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fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata,
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fn->busy, fn->abort, fn->post);
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#ifdef CFG_FPGA_PROG_FEEDBACK
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printf ("Initializing FPGA Device %d...\n", cookie);
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#endif
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/*
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* Run the pre configuration function if there is one.
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*/
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if (*fn->pre) {
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(*fn->pre) (cookie);
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}
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/*
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* Assert the program line. The minimum pulse width for
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* Virtex II devices is 300 nS (Tprogram parameter in datasheet).
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* There is no maximum value for the pulse width. Check to make
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* sure that INIT_B goes low after assertion of PROG_B
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*/
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(*fn->pgm) (TRUE, TRUE, cookie);
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udelay (10);
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ts = get_timer (0);
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do {
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if (get_timer (ts) > CFG_FPGA_WAIT_INIT) {
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printf ("%s:%d: ** Timeout after %d ticks waiting for INIT"
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" to assert.\n", __FUNCTION__, __LINE__,
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CFG_FPGA_WAIT_INIT);
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(*fn->abort) (cookie);
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return FPGA_FAIL;
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}
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} while (!(*fn->init) (cookie));
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(*fn->pgm) (FALSE, TRUE, cookie);
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CONFIG_FPGA_DELAY ();
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(*fn->clk) (TRUE, TRUE, cookie);
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/*
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* Start a timer and wait for INIT_B to go high
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*/
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ts = get_timer (0);
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do {
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CONFIG_FPGA_DELAY ();
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if (get_timer (ts) > CFG_FPGA_WAIT_INIT) {
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printf ("%s:%d: ** Timeout after %d ticks waiting for INIT"
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" to deassert.\n", __FUNCTION__, __LINE__,
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CFG_FPGA_WAIT_INIT);
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(*fn->abort) (cookie);
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return FPGA_FAIL;
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}
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} while ((*fn->init) (cookie) && (*fn->busy) (cookie));
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(*fn->wr) (TRUE, TRUE, cookie);
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(*fn->cs) (TRUE, TRUE, cookie);
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udelay (10000);
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/*
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* Load the data byte by byte
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*/
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while (bytecount < bsize) {
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#ifdef CFG_FPGA_CHECK_CTRLC
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if (ctrlc ()) {
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(*fn->abort) (cookie);
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return FPGA_FAIL;
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}
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#endif
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if ((*fn->done) (cookie) == FPGA_SUCCESS) {
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PRINTF ("%s:%d:done went active early, bytecount = %d\n",
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__FUNCTION__, __LINE__, bytecount);
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break;
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}
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#ifdef CFG_FPGA_CHECK_ERROR
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if ((*fn->init) (cookie)) {
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printf ("\n%s:%d: ** Error: INIT asserted during"
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" configuration\n", __FUNCTION__, __LINE__);
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printf ("%d = buffer offset, %d = buffer size\n",
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bytecount, bsize);
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(*fn->abort) (cookie);
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return FPGA_FAIL;
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}
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#endif
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(*fn->wdata) (data[bytecount++], TRUE, cookie);
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CONFIG_FPGA_DELAY ();
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/*
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* Cycle the clock pin
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*/
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(*fn->clk) (FALSE, TRUE, cookie);
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CONFIG_FPGA_DELAY ();
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(*fn->clk) (TRUE, TRUE, cookie);
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#ifdef CFG_FPGA_CHECK_BUSY
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ts = get_timer (0);
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while ((*fn->busy) (cookie)) {
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if (get_timer (ts) > CFG_FPGA_WAIT_BUSY) {
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printf ("%s:%d: ** Timeout after %d ticks waiting for"
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" BUSY to deassert\n",
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__FUNCTION__, __LINE__, CFG_FPGA_WAIT_BUSY);
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(*fn->abort) (cookie);
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return FPGA_FAIL;
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}
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}
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#endif
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#ifdef CFG_FPGA_PROG_FEEDBACK
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if (bytecount % (bsize / 40) == 0)
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putc ('.');
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#endif
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}
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/*
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* Finished writing the data; deassert FPGA CS_B and WRITE_B signals.
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*/
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CONFIG_FPGA_DELAY ();
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(*fn->cs) (FALSE, TRUE, cookie);
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(*fn->wr) (FALSE, TRUE, cookie);
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#ifdef CFG_FPGA_PROG_FEEDBACK
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putc ('\n');
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#endif
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/*
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* Check for successful configuration. FPGA INIT_B and DONE should
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* both be high upon successful configuration.
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*/
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ts = get_timer (0);
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ret_val = FPGA_SUCCESS;
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while (((*fn->done) (cookie) == FPGA_FAIL) || (*fn->init) (cookie)) {
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if (get_timer (ts) > CFG_FPGA_WAIT_CONFIG) {
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printf ("%s:%d: ** Timeout after %d ticks waiting for DONE to"
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"assert and INIT to deassert\n",
|
||
|
|
__FUNCTION__, __LINE__, CFG_FPGA_WAIT_CONFIG);
|
||
|
|
(*fn->abort) (cookie);
|
||
|
|
ret_val = FPGA_FAIL;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (ret_val == FPGA_SUCCESS) {
|
||
|
|
#ifdef CFG_FPGA_PROG_FEEDBACK
|
||
|
|
printf ("Initialization of FPGA device %d complete\n", cookie);
|
||
|
|
#endif
|
||
|
|
/*
|
||
|
|
* Run the post configuration function if there is one.
|
||
|
|
*/
|
||
|
|
if (*fn->post) {
|
||
|
|
(*fn->post) (cookie);
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
#ifdef CFG_FPGA_PROG_FEEDBACK
|
||
|
|
printf ("** Initialization of FPGA device %d FAILED\n",
|
||
|
|
cookie);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
printf ("%s:%d: NULL Interface function table!\n",
|
||
|
|
__FUNCTION__, __LINE__);
|
||
|
|
}
|
||
|
|
return ret_val;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Read the FPGA configuration data
|
||
|
|
*/
|
||
|
|
static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize)
|
||
|
|
{
|
||
|
|
int ret_val = FPGA_FAIL;
|
||
|
|
Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns;
|
||
|
|
|
||
|
|
if (fn) {
|
||
|
|
unsigned char *data = (unsigned char *) buf;
|
||
|
|
size_t bytecount = 0;
|
||
|
|
int cookie = desc->cookie;
|
||
|
|
|
||
|
|
printf ("Starting Dump of FPGA Device %d...\n", cookie);
|
||
|
|
|
||
|
|
(*fn->cs) (TRUE, TRUE, cookie);
|
||
|
|
(*fn->clk) (TRUE, TRUE, cookie);
|
||
|
|
|
||
|
|
while (bytecount < bsize) {
|
||
|
|
#ifdef CFG_FPGA_CHECK_CTRLC
|
||
|
|
if (ctrlc ()) {
|
||
|
|
(*fn->abort) (cookie);
|
||
|
|
return FPGA_FAIL;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
/*
|
||
|
|
* Cycle the clock and read the data
|
||
|
|
*/
|
||
|
|
(*fn->clk) (FALSE, TRUE, cookie);
|
||
|
|
(*fn->clk) (TRUE, TRUE, cookie);
|
||
|
|
(*fn->rdata) (&(data[bytecount++]), cookie);
|
||
|
|
#ifdef CFG_FPGA_PROG_FEEDBACK
|
||
|
|
if (bytecount % (bsize / 40) == 0)
|
||
|
|
putc ('.');
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Deassert CS_B and cycle the clock to deselect the device.
|
||
|
|
*/
|
||
|
|
(*fn->cs) (FALSE, FALSE, cookie);
|
||
|
|
(*fn->clk) (FALSE, TRUE, cookie);
|
||
|
|
(*fn->clk) (TRUE, TRUE, cookie);
|
||
|
|
|
||
|
|
#ifdef CFG_FPGA_PROG_FEEDBACK
|
||
|
|
putc ('\n');
|
||
|
|
#endif
|
||
|
|
puts ("Done.\n");
|
||
|
|
} else {
|
||
|
|
printf ("%s:%d: NULL Interface function table!\n",
|
||
|
|
__FUNCTION__, __LINE__);
|
||
|
|
}
|
||
|
|
return ret_val;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Relocate the addresses in the function table from FLASH (or ROM,
|
||
|
|
* or whatever) to RAM.
|
||
|
|
*/
|
||
|
|
static int Virtex2_ssm_reloc (Xilinx_desc * desc, ulong reloc_offset)
|
||
|
|
{
|
||
|
|
ulong addr;
|
||
|
|
int ret_val = FPGA_FAIL;
|
||
|
|
Xilinx_Virtex2_Slave_SelectMap_fns *fn_r, *fn =
|
||
|
|
(Xilinx_Virtex2_Slave_SelectMap_fns *) (desc->iface_fns);
|
||
|
|
|
||
|
|
if (fn) {
|
||
|
|
/*
|
||
|
|
* Get the relocated table address
|
||
|
|
*/
|
||
|
|
addr = (ulong) fn + reloc_offset;
|
||
|
|
fn_r = (Xilinx_Virtex2_Slave_SelectMap_fns *) addr;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Check to see if the table has already been relocated. If not, do
|
||
|
|
* a sanity check to make sure there is a faithful copy of the
|
||
|
|
* FLASH based function table in RAM, then adjust the table.
|
||
|
|
*/
|
||
|
|
if (!fn_r->relocated) {
|
||
|
|
if (memcmp
|
||
|
|
(fn_r, fn, sizeof (Xilinx_Virtex2_Slave_SelectMap_fns))
|
||
|
|
== 0) {
|
||
|
|
desc->iface_fns = fn_r;
|
||
|
|
} else {
|
||
|
|
PRINTF ("%s:%d: Invalid function table at 0x%p\n",
|
||
|
|
__FUNCTION__, __LINE__, fn_r);
|
||
|
|
return FPGA_FAIL;
|
||
|
|
}
|
||
|
|
|
||
|
|
PRINTF ("%s:%d: Relocating descriptor at 0x%p\n",
|
||
|
|
__FUNCTION__, __LINE__, desc);
|
||
|
|
|
||
|
|
addr = (ulong) (fn->pre) + reloc_offset;
|
||
|
|
fn_r->pre = (Xilinx_pre_fn) addr;
|
||
|
|
addr = (ulong) (fn->pgm) + reloc_offset;
|
||
|
|
fn_r->pgm = (Xilinx_pgm_fn) addr;
|
||
|
|
addr = (ulong) (fn->init) + reloc_offset;
|
||
|
|
fn_r->init = (Xilinx_init_fn) addr;
|
||
|
|
addr = (ulong) (fn->done) + reloc_offset;
|
||
|
|
fn_r->done = (Xilinx_done_fn) addr;
|
||
|
|
addr = (ulong) (fn->err) + reloc_offset;
|
||
|
|
fn_r->err = (Xilinx_err_fn) addr;
|
||
|
|
addr = (ulong) (fn->clk) + reloc_offset;
|
||
|
|
fn_r->clk = (Xilinx_clk_fn) addr;
|
||
|
|
addr = (ulong) (fn->cs) + reloc_offset;
|
||
|
|
fn_r->cs = (Xilinx_cs_fn) addr;
|
||
|
|
addr = (ulong) (fn->wr) + reloc_offset;
|
||
|
|
fn_r->wr = (Xilinx_wr_fn) addr;
|
||
|
|
addr = (ulong) (fn->rdata) + reloc_offset;
|
||
|
|
fn_r->rdata = (Xilinx_rdata_fn) addr;
|
||
|
|
addr = (ulong) (fn->wdata) + reloc_offset;
|
||
|
|
fn_r->wdata = (Xilinx_wdata_fn) addr;
|
||
|
|
addr = (ulong) (fn->busy) + reloc_offset;
|
||
|
|
fn_r->busy = (Xilinx_busy_fn) addr;
|
||
|
|
addr = (ulong) (fn->abort) + reloc_offset;
|
||
|
|
fn_r->abort = (Xilinx_abort_fn) addr;
|
||
|
|
addr = (ulong) (fn->post) + reloc_offset;
|
||
|
|
fn_r->post = (Xilinx_post_fn) addr;
|
||
|
|
fn_r->relocated = TRUE;
|
||
|
|
} else {
|
||
|
|
printf ("%s:%d: Function table @0x%p has already been relocated\n", __FUNCTION__, __LINE__, fn_r);
|
||
|
|
desc->iface_fns = fn_r;
|
||
|
|
}
|
||
|
|
ret_val = FPGA_SUCCESS;
|
||
|
|
} else {
|
||
|
|
printf ("%s: NULL Interface function table!\n", __FUNCTION__);
|
||
|
|
}
|
||
|
|
return ret_val;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int Virtex2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
|
||
|
|
{
|
||
|
|
printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__);
|
||
|
|
return FPGA_FAIL;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int Virtex2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize)
|
||
|
|
{
|
||
|
|
printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__);
|
||
|
|
return FPGA_FAIL;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int Virtex2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset)
|
||
|
|
{
|
||
|
|
int ret_val = FPGA_FAIL;
|
||
|
|
Xilinx_Virtex2_Slave_Serial_fns *fn =
|
||
|
|
(Xilinx_Virtex2_Slave_Serial_fns *) (desc->iface_fns);
|
||
|
|
|
||
|
|
if (fn) {
|
||
|
|
printf ("%s:%d: Slave Serial Loading is unsupported\n",
|
||
|
|
__FUNCTION__, __LINE__);
|
||
|
|
} else {
|
||
|
|
printf ("%s:%d: NULL Interface function table!\n",
|
||
|
|
__FUNCTION__, __LINE__);
|
||
|
|
}
|
||
|
|
return ret_val;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* vim: set ts=4 tw=78: */
|