211 lines
10 KiB
C
211 lines
10 KiB
C
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/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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This software file (the "File") is owned and distributed by Marvell
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International Ltd. and/or its affiliates ("Marvell") under the following
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alternative licensing terms. Once you have made an election to distribute the
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File under one of the following license alternatives, please (i) delete this
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introductory statement regarding license alternatives, (ii) delete the two
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license alternatives that you have not elected to use and (iii) preserve the
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Marvell copyright notice above.
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********************************************************************************
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Marvell Commercial License Option
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If you received this File from Marvell and you have entered into a commercial
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license agreement (a "Commercial License") with Marvell, the File is licensed
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to you under the terms of the applicable Commercial License.
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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********************************************************************************
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Marvell BSD License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File under the following licensing terms.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Marvell nor the names of its contributors may be
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used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#ifndef __INCmvIdmaSpech
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#define __INCmvIdmaSpech
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/* defines */
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/* IDMA channel rgisters */
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#define IDMA_BYTE_COUNT_REG(chan) (IDMA_UNIT_BASE + 0x0 + ((chan) * 4))
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#define IDMA_SRC_ADDR_REG(chan) (IDMA_UNIT_BASE + 0x10 + ((chan) * 4))
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#define IDMA_DST_ADDR_REG(chan) (IDMA_UNIT_BASE + 0x20 + ((chan) * 4))
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#define IDMA_NEXT_DESC_PTR_REG(chan) (IDMA_UNIT_BASE + 0x30 + ((chan) * 4))
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#define IDMA_CURR_DESC_PTR_REG(chan) (IDMA_UNIT_BASE + 0x70 + ((chan) * 4))
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/* IDMA Channel Control */
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#define IDMA_CTRL_LOW_REG(chan) (IDMA_UNIT_BASE + 0x40 + ((chan) * 4))
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#define IDMA_CTRL_HIGH_REG(chan) (IDMA_UNIT_BASE + 0x80 + ((chan) * 4))
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/* IDMA Interrupt Register */
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#define IDMA_CAUSE_REG (IDMA_UNIT_BASE + 0xc0)
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#define IDMA_MASK_REG (IDMA_UNIT_BASE + 0xc4)
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#define IDMA_ERROR_ADDR_REG (IDMA_UNIT_BASE + 0xc8)
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#define IDMA_ERROR_SELECT_REG (IDMA_UNIT_BASE + 0xcc)
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/* DMA register fileds */
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/* IDMA Channel Byte Count Register (ICBCR) */
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#define ICBCR_BYTECNT_OFFS 0 /* Byte count field offset */
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#define ICBCR_BYTECNT_MASK_64K 0xFFFF /* Maximum Byte count for 64K */
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#define ICBCR_BYTECNT_MASK_16M 0xFFFFFF/* Maximum Byte count for 16M */
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#define ICBCR_BYTECNT_LEFT_OFFS 30 /* Applicable for 16M mode */
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#define ICBCR_BYTECNT_LEFT (1 << ICBCR_BYTECNT_LEFT_OFFS)
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#define ICBCR_DESC_OWNER_OFFS 31 /* Descriptor owned by DMA/CPU */
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#define ICBCR_DESC_OWNER_MASK (1 << ICBCR_DESC_OWNER_OFFS)
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#define ICBCR_DESC_OWNER_BY_DMA (0 << ICBCR_DESC_OWNER_OFFS)
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#define ICBCR_DESC_OWNED_BY_CPU (1 << ICBCR_DESC_OWNER_OFFS)
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/* IDMA Channel Control Low Register (ICCLR) */
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/* Data Transfer Limit Note: If an IDMA accesses a cache coherent DRAM */
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/* region, the burst limit must not exceed 32 bytes. */
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#define B_8BYTE 0
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#define B_16BYTE 1
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#define B_32BYTE 3
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#define B_64BYTE 7
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#define B_128BYTE 4
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#define ICCLR_DST_BURST_LIM_OFFS 0
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#define ICCLR_DST_BURST_LIM_MASK (0x7 << ICCLR_DST_BURST_LIM_OFFS)
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#define ICCLR_DST_BURST_LIM_8BYTE (B_8BYTE << ICCLR_DST_BURST_LIM_OFFS)
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#define ICCLR_DST_BURST_LIM_16BYTE (B_16BYTE << ICCLR_DST_BURST_LIM_OFFS)
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#define ICCLR_DST_BURST_LIM_32BYTE (B_32BYTE << ICCLR_DST_BURST_LIM_OFFS)
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#define ICCLR_DST_BURST_LIM_64BYTE (B_64BYTE << ICCLR_DST_BURST_LIM_OFFS)
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#define ICCLR_DST_BURST_LIM_128BYTE (B_128BYTE << ICCLR_DST_BURST_LIM_OFFS)
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#define ICCLR_SRC_HOLD_OFFS 3 /* Hold/increment source address*/
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#define ICCLR_SRC_HOLD_MASK (1 << ICCLR_SRC_HOLD_OFFS)
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#define ICCLR_SRC_INC (0 << ICCLR_SRC_HOLD_OFFS)
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#define ICCLR_SRC_HOLD (1 << ICCLR_SRC_HOLD_OFFS)
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#define ICCLR_ACK_WIDTH_OFFS 4 /* Asserted for one/two TCLK cycle */
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#define ICCLR_ACK_WIDTH_MASK (1 << ICCLR_ACK_WIDTH_OFFS)
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#define ICCLR_ACK_WIDTH_ONE_TCLK (0 << ICCLR_ACK_WIDTH_OFFS)
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#define ICCLR_ACK_WIDTH_TWO_TCLK (1 << ICCLR_ACK_WIDTH_OFFS)
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#define ICCLR_DST_HOLD_OFFS 5 /* Hold/increment source address*/
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#define ICCLR_DST_HOLD_MASK (1 << ICCLR_DST_HOLD_OFFS)
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#define ICCLR_DST_INC (0 << ICCLR_DST_HOLD_OFFS)
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#define ICCLR_DST_HOLD (1 << ICCLR_DST_HOLD_OFFS)
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#define ICCLR_SRC_BURST_LIM_OFFS 6
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#define ICCLR_SRC_BURST_LIM_MASK (0x7 << ICCLR_SRC_BURST_LIM_OFFS)
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#define ICCLR_SRC_BURST_LIM_8BYTE (B_8BYTE << ICCLR_SRC_BURST_LIM_OFFS)
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#define ICCLR_SRC_BURST_LIM_16BYTE (B_16BYTE << ICCLR_SRC_BURST_LIM_OFFS)
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#define ICCLR_SRC_BURST_LIM_32BYTE (B_32BYTE << ICCLR_SRC_BURST_LIM_OFFS)
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#define ICCLR_SRC_BURST_LIM_64BYTE (B_64BYTE << ICCLR_SRC_BURST_LIM_OFFS)
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#define ICCLR_SRC_BURST_LIM_128BYTE (B_128BYTE << ICCLR_SRC_BURST_LIM_OFFS)
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#define ICCLR_CHAIN_MODE_OFFS 9
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#define ICCLR_NON_CHAIN_MODE (1 << ICCLR_CHAIN_MODE_OFFS)
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#define ICCLR_INT_MODE_OFFS 10 /* Interrupt mode */
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#define ICCLR_INT_MODE_MASK (1 << ICCLR_INT_MODE_OFFS)
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#define ICCLR_INT_BYTE_CNT_ZERO (0 << ICCLR_INT_MODE_OFFS)
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#define ICCLR_INT_EVERY_NULL_PTR (1 << ICCLR_INT_MODE_OFFS)
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#define ICCLR_DEMAND_MODE_OFFS 11 /* Demand/Block transfer mode */
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#define ICCLR_DEMAND_MODE_MASK (1 << ICCLR_DEMAND_MODE_OFFS)
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#define ICCLR_DEMAND_MODE (0 << ICCLR_DEMAND_MODE_OFFS)
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#define ICCLR_BLOCK_MODE (1 << ICCLR_DEMAND_MODE_OFFS)
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#define ICCLR_CHAN_ENABLE BIT12 /* Channel enable */
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#define ICCLR_FETCH_NEXT_DESC BIT13 /* Fetch next descriptor */
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#define ICCLR_CHAN_ACTIVE BIT14 /* Channel active */
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#define ICCLR_REQ_DIR_OFFS 15 /* Request generated by src/dst */
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#define ICCLR_REQ_DIR_MASK (1 << ICCLR_REQ_DIR_OFFS)
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#define ICCLR_REQ_DIR_SRC (0 << ICCLR_REQ_DIR_OFFS)
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#define ICCLR_REQ_DIR_DST (1 << ICCLR_REQ_DIR_OFFS)
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#define ICCLR_REQ_MODE_OFFS 16 /* DMAReqn is level/edge input */
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#define ICCLR_REQ_MODE_MASK (1 << ICCLR_REQ_MODE_OFFS)
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#define ICCLR_REQ_MODE_LEVEL (0 << ICCLR_REQ_MODE_OFFS)
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#define ICCLR_REQ_MODE_EDGE (1 << ICCLR_REQ_MODE_OFFS)
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#define ICCLR_CLOSE_DESC_ENABLE BIT17 /* Close descriptor enable */
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#define ICCLR_EOT_ENABLE BIT18 /* End Of Tarnsfer (EOT) enable */
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#define ICCLR_EOT_AFFECT_OFFS 19 /* EOT -> Fetch next descriptor/halt */
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#define ICCLR_EOT_AFFECT_MASK (1 << ICCLR_EOT_AFFECT_OFFS)
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#define ICCLR_EOT_FETCH_NEXT (0 << ICCLR_EOT_AFFECT_OFFS)
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#define ICCLR_EOT_FETCH_HALT (1 << ICCLR_EOT_AFFECT_OFFS)
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#define ICCLR_CHANNEL_ABORT BIT20 /* Abort DMA transfer */
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#define ICCLR_OVRRD_SRC_OFFS 21
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#define ICCLR_OVRRD_SRC_MASK (0x3 << ICCLR_OVRRD_SRC_OFFS)
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#define ICCLR_OVRRD_SRC_BAR(barNo) ((barNo) << ICCLR_OVRRD_SRC_OFFS)
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#define ICCLR_OVRRD_DST_OFFS 23
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#define ICCLR_OVRRD_DST_MASK (0x3 << ICCLR_OVRRD_DST_OFFS)
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#define ICCLR_OVRRD_DST_BAR(barNo) ((barNo) << ICCLR_OVRRD_DST_OFFS)
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#define ICCLR_OVRRD_NDSC_OFFS 25
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#define ICCLR_OVRRD_NDSC_MASK (0x3 << ICCLR_OVRRD_NDSC_OFFS)
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#define ICCLR_OVRRD_NDSC_BAR(barNo) ((barNo) << ICCLR_OVRRD_NDSC_OFFS)
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#define ICCLR_DESC_MODE_OFFS 31 /* Descriptor mode 64KB/16M */
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#define ICCLR_DESC_MODE_MASK (1 << ICCLR_DESC_MODE_OFFS)
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#define ICCLR_DESC_MODE_64K (0 << ICCLR_DESC_MODE_OFFS)
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#define ICCLR_DESC_MODE_16M (1 << ICCLR_DESC_MODE_OFFS)
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/* IDMA Channel Control High Register (ICCHR) */
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#define ICCHR_ENDIANESS_OFFS 0
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#define ICCHR_ENDIANESS_MASK (1 << ICCHR_ENDIANESS_OFFS)
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#define ICCHR_ENDIAN_BIG (0 << ICCHR_ENDIANESS_OFFS)
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#define ICCHR_ENDIAN_LITTLE (1 << ICCHR_ENDIANESS_OFFS)
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#define ICCHR_DESC_BYTE_SWAP_EN BIT1 /* swap the bytes of 64-bit */
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/* dword during descriptor fetch*/
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#define ICCHR_DESC_DEMAND_ENABLE BIT2 /* Descriptor Demand Mode en */
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/* IDMA Channel Interrupt Cause Register (ICICR) */
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#define ICICR_CHAN_OFFS 8
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#define ICICR_CAUSE_OFFS(chan) (chan * ICICR_CHAN_OFFS)
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#define ICICR_CAUSE_MASK_ALL(chan) (0xFF << ICICR_CAUSE_OFFS(chan))
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#define ICICR_CAUSE_MASK(chan, cause) (1 << (cause + ICICR_CAUSE_OFFS(chan)))
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#define ICICR_COMP_MASK 0x01010101
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#define ICICR_ERR_MASK 0x3e3e3e3e
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/* IDMA Error Select Register (IESR) */
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#define IESR_ERR_TYPE_OFFS 0
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#define IESR_ERR_TYPE_MASK (0x1f << IESR_ERR_TYPE_OFFS)
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#endif /* __INCmvIdmaSpech */
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