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uboot-1.1.4-kirkwood/board/mv_feroceon/mv_hal/idma/mvIdmaRegs.h

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10 KiB
C

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*******************************************************************************/
#ifndef __INCmvIdmaSpech
#define __INCmvIdmaSpech
/* defines */
/* IDMA channel rgisters */
#define IDMA_BYTE_COUNT_REG(chan) (IDMA_UNIT_BASE + 0x0 + ((chan) * 4))
#define IDMA_SRC_ADDR_REG(chan) (IDMA_UNIT_BASE + 0x10 + ((chan) * 4))
#define IDMA_DST_ADDR_REG(chan) (IDMA_UNIT_BASE + 0x20 + ((chan) * 4))
#define IDMA_NEXT_DESC_PTR_REG(chan) (IDMA_UNIT_BASE + 0x30 + ((chan) * 4))
#define IDMA_CURR_DESC_PTR_REG(chan) (IDMA_UNIT_BASE + 0x70 + ((chan) * 4))
/* IDMA Channel Control */
#define IDMA_CTRL_LOW_REG(chan) (IDMA_UNIT_BASE + 0x40 + ((chan) * 4))
#define IDMA_CTRL_HIGH_REG(chan) (IDMA_UNIT_BASE + 0x80 + ((chan) * 4))
/* IDMA Interrupt Register */
#define IDMA_CAUSE_REG (IDMA_UNIT_BASE + 0xc0)
#define IDMA_MASK_REG (IDMA_UNIT_BASE + 0xc4)
#define IDMA_ERROR_ADDR_REG (IDMA_UNIT_BASE + 0xc8)
#define IDMA_ERROR_SELECT_REG (IDMA_UNIT_BASE + 0xcc)
/* DMA register fileds */
/* IDMA Channel Byte Count Register (ICBCR) */
#define ICBCR_BYTECNT_OFFS 0 /* Byte count field offset */
#define ICBCR_BYTECNT_MASK_64K 0xFFFF /* Maximum Byte count for 64K */
#define ICBCR_BYTECNT_MASK_16M 0xFFFFFF/* Maximum Byte count for 16M */
#define ICBCR_BYTECNT_LEFT_OFFS 30 /* Applicable for 16M mode */
#define ICBCR_BYTECNT_LEFT (1 << ICBCR_BYTECNT_LEFT_OFFS)
#define ICBCR_DESC_OWNER_OFFS 31 /* Descriptor owned by DMA/CPU */
#define ICBCR_DESC_OWNER_MASK (1 << ICBCR_DESC_OWNER_OFFS)
#define ICBCR_DESC_OWNER_BY_DMA (0 << ICBCR_DESC_OWNER_OFFS)
#define ICBCR_DESC_OWNED_BY_CPU (1 << ICBCR_DESC_OWNER_OFFS)
/* IDMA Channel Control Low Register (ICCLR) */
/* Data Transfer Limit Note: If an IDMA accesses a cache coherent DRAM */
/* region, the burst limit must not exceed 32 bytes. */
#define B_8BYTE 0
#define B_16BYTE 1
#define B_32BYTE 3
#define B_64BYTE 7
#define B_128BYTE 4
#define ICCLR_DST_BURST_LIM_OFFS 0
#define ICCLR_DST_BURST_LIM_MASK (0x7 << ICCLR_DST_BURST_LIM_OFFS)
#define ICCLR_DST_BURST_LIM_8BYTE (B_8BYTE << ICCLR_DST_BURST_LIM_OFFS)
#define ICCLR_DST_BURST_LIM_16BYTE (B_16BYTE << ICCLR_DST_BURST_LIM_OFFS)
#define ICCLR_DST_BURST_LIM_32BYTE (B_32BYTE << ICCLR_DST_BURST_LIM_OFFS)
#define ICCLR_DST_BURST_LIM_64BYTE (B_64BYTE << ICCLR_DST_BURST_LIM_OFFS)
#define ICCLR_DST_BURST_LIM_128BYTE (B_128BYTE << ICCLR_DST_BURST_LIM_OFFS)
#define ICCLR_SRC_HOLD_OFFS 3 /* Hold/increment source address*/
#define ICCLR_SRC_HOLD_MASK (1 << ICCLR_SRC_HOLD_OFFS)
#define ICCLR_SRC_INC (0 << ICCLR_SRC_HOLD_OFFS)
#define ICCLR_SRC_HOLD (1 << ICCLR_SRC_HOLD_OFFS)
#define ICCLR_ACK_WIDTH_OFFS 4 /* Asserted for one/two TCLK cycle */
#define ICCLR_ACK_WIDTH_MASK (1 << ICCLR_ACK_WIDTH_OFFS)
#define ICCLR_ACK_WIDTH_ONE_TCLK (0 << ICCLR_ACK_WIDTH_OFFS)
#define ICCLR_ACK_WIDTH_TWO_TCLK (1 << ICCLR_ACK_WIDTH_OFFS)
#define ICCLR_DST_HOLD_OFFS 5 /* Hold/increment source address*/
#define ICCLR_DST_HOLD_MASK (1 << ICCLR_DST_HOLD_OFFS)
#define ICCLR_DST_INC (0 << ICCLR_DST_HOLD_OFFS)
#define ICCLR_DST_HOLD (1 << ICCLR_DST_HOLD_OFFS)
#define ICCLR_SRC_BURST_LIM_OFFS 6
#define ICCLR_SRC_BURST_LIM_MASK (0x7 << ICCLR_SRC_BURST_LIM_OFFS)
#define ICCLR_SRC_BURST_LIM_8BYTE (B_8BYTE << ICCLR_SRC_BURST_LIM_OFFS)
#define ICCLR_SRC_BURST_LIM_16BYTE (B_16BYTE << ICCLR_SRC_BURST_LIM_OFFS)
#define ICCLR_SRC_BURST_LIM_32BYTE (B_32BYTE << ICCLR_SRC_BURST_LIM_OFFS)
#define ICCLR_SRC_BURST_LIM_64BYTE (B_64BYTE << ICCLR_SRC_BURST_LIM_OFFS)
#define ICCLR_SRC_BURST_LIM_128BYTE (B_128BYTE << ICCLR_SRC_BURST_LIM_OFFS)
#define ICCLR_CHAIN_MODE_OFFS 9
#define ICCLR_NON_CHAIN_MODE (1 << ICCLR_CHAIN_MODE_OFFS)
#define ICCLR_INT_MODE_OFFS 10 /* Interrupt mode */
#define ICCLR_INT_MODE_MASK (1 << ICCLR_INT_MODE_OFFS)
#define ICCLR_INT_BYTE_CNT_ZERO (0 << ICCLR_INT_MODE_OFFS)
#define ICCLR_INT_EVERY_NULL_PTR (1 << ICCLR_INT_MODE_OFFS)
#define ICCLR_DEMAND_MODE_OFFS 11 /* Demand/Block transfer mode */
#define ICCLR_DEMAND_MODE_MASK (1 << ICCLR_DEMAND_MODE_OFFS)
#define ICCLR_DEMAND_MODE (0 << ICCLR_DEMAND_MODE_OFFS)
#define ICCLR_BLOCK_MODE (1 << ICCLR_DEMAND_MODE_OFFS)
#define ICCLR_CHAN_ENABLE BIT12 /* Channel enable */
#define ICCLR_FETCH_NEXT_DESC BIT13 /* Fetch next descriptor */
#define ICCLR_CHAN_ACTIVE BIT14 /* Channel active */
#define ICCLR_REQ_DIR_OFFS 15 /* Request generated by src/dst */
#define ICCLR_REQ_DIR_MASK (1 << ICCLR_REQ_DIR_OFFS)
#define ICCLR_REQ_DIR_SRC (0 << ICCLR_REQ_DIR_OFFS)
#define ICCLR_REQ_DIR_DST (1 << ICCLR_REQ_DIR_OFFS)
#define ICCLR_REQ_MODE_OFFS 16 /* DMAReqn is level/edge input */
#define ICCLR_REQ_MODE_MASK (1 << ICCLR_REQ_MODE_OFFS)
#define ICCLR_REQ_MODE_LEVEL (0 << ICCLR_REQ_MODE_OFFS)
#define ICCLR_REQ_MODE_EDGE (1 << ICCLR_REQ_MODE_OFFS)
#define ICCLR_CLOSE_DESC_ENABLE BIT17 /* Close descriptor enable */
#define ICCLR_EOT_ENABLE BIT18 /* End Of Tarnsfer (EOT) enable */
#define ICCLR_EOT_AFFECT_OFFS 19 /* EOT -> Fetch next descriptor/halt */
#define ICCLR_EOT_AFFECT_MASK (1 << ICCLR_EOT_AFFECT_OFFS)
#define ICCLR_EOT_FETCH_NEXT (0 << ICCLR_EOT_AFFECT_OFFS)
#define ICCLR_EOT_FETCH_HALT (1 << ICCLR_EOT_AFFECT_OFFS)
#define ICCLR_CHANNEL_ABORT BIT20 /* Abort DMA transfer */
#define ICCLR_OVRRD_SRC_OFFS 21
#define ICCLR_OVRRD_SRC_MASK (0x3 << ICCLR_OVRRD_SRC_OFFS)
#define ICCLR_OVRRD_SRC_BAR(barNo) ((barNo) << ICCLR_OVRRD_SRC_OFFS)
#define ICCLR_OVRRD_DST_OFFS 23
#define ICCLR_OVRRD_DST_MASK (0x3 << ICCLR_OVRRD_DST_OFFS)
#define ICCLR_OVRRD_DST_BAR(barNo) ((barNo) << ICCLR_OVRRD_DST_OFFS)
#define ICCLR_OVRRD_NDSC_OFFS 25
#define ICCLR_OVRRD_NDSC_MASK (0x3 << ICCLR_OVRRD_NDSC_OFFS)
#define ICCLR_OVRRD_NDSC_BAR(barNo) ((barNo) << ICCLR_OVRRD_NDSC_OFFS)
#define ICCLR_DESC_MODE_OFFS 31 /* Descriptor mode 64KB/16M */
#define ICCLR_DESC_MODE_MASK (1 << ICCLR_DESC_MODE_OFFS)
#define ICCLR_DESC_MODE_64K (0 << ICCLR_DESC_MODE_OFFS)
#define ICCLR_DESC_MODE_16M (1 << ICCLR_DESC_MODE_OFFS)
/* IDMA Channel Control High Register (ICCHR) */
#define ICCHR_ENDIANESS_OFFS 0
#define ICCHR_ENDIANESS_MASK (1 << ICCHR_ENDIANESS_OFFS)
#define ICCHR_ENDIAN_BIG (0 << ICCHR_ENDIANESS_OFFS)
#define ICCHR_ENDIAN_LITTLE (1 << ICCHR_ENDIANESS_OFFS)
#define ICCHR_DESC_BYTE_SWAP_EN BIT1 /* swap the bytes of 64-bit */
/* dword during descriptor fetch*/
#define ICCHR_DESC_DEMAND_ENABLE BIT2 /* Descriptor Demand Mode en */
/* IDMA Channel Interrupt Cause Register (ICICR) */
#define ICICR_CHAN_OFFS 8
#define ICICR_CAUSE_OFFS(chan) (chan * ICICR_CHAN_OFFS)
#define ICICR_CAUSE_MASK_ALL(chan) (0xFF << ICICR_CAUSE_OFFS(chan))
#define ICICR_CAUSE_MASK(chan, cause) (1 << (cause + ICICR_CAUSE_OFFS(chan)))
#define ICICR_COMP_MASK 0x01010101
#define ICICR_ERR_MASK 0x3e3e3e3e
/* IDMA Error Select Register (IESR) */
#define IESR_ERR_TYPE_OFFS 0
#define IESR_ERR_TYPE_MASK (0x1f << IESR_ERR_TYPE_OFFS)
#endif /* __INCmvIdmaSpech */