458 lines
16 KiB
ArmAsm
458 lines
16 KiB
ArmAsm
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/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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This software file (the "File") is owned and distributed by Marvell
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International Ltd. and/or its affiliates ("Marvell") under the following
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alternative licensing terms. Once you have made an election to distribute the
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File under one of the following license alternatives, please (i) delete this
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introductory statement regarding license alternatives, (ii) delete the two
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license alternatives that you have not elected to use and (iii) preserve the
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Marvell copyright notice above.
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********************************************************************************
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Marvell Commercial License Option
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If you received this File from Marvell and you have entered into a commercial
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license agreement (a "Commercial License") with Marvell, the File is licensed
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to you under the terms of the applicable Commercial License.
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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********************************************************************************
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Marvell BSD License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File under the following licensing terms.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Marvell nor the names of its contributors may be
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used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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/* includes */
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#define MV_ASMLANGUAGE
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#include "ctrlEnv/mvCtrlEnvSpec.h"
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#include "boardEnv/mvBoardEnvSpec.h"
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#include "mvOsAsm.h"
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#include "mvTwsiSpec.h"
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#include "mvSysHwConfig.h"
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#include "ctrlEnv/sys/mvCpuIfRegs.h"
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#include "mvCommon.h"
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#define I2C_CH MV_BOARD_DIMM_I2C_CHANNEL
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/* defines */
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/* defines */
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.data
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.global _i2cInit
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.global _i2cRead
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.text
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/*******************************************************************************
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* _i2cInit - Initialize TWSI interface
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*
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* DESCRIPTION:
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* The function performs TWSI interface initialization. It resets the
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* TWSI state machine and initialize its clock to 100KHz assuming Tclock
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* of 133MHz.
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*
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* INPUT:
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* None.
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*
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* OUTPUT:
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* None.
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*
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* RETURN:
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* None.
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*
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*******************************************************************************/
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_i2cInit:
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mov r9, LR /* Save link register */
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mov r0, #0 /* Make sure r0 is zero */
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/* Reset the i2c Mechanism first */
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MV_REG_WRITE_ASM (r0, r1, TWSI_SOFT_RESET_REG(I2C_CH))
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bl _twsiDelay
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bl _twsiDelay
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/* Initializing the I2C mechanism. Assuming Tclock frequency */
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/* of 166MHz. The I2C frequency in that case will be 100KHz. */
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/* For this settings, M = 9 and N = 3. Set the baud-rate with the */
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/* value of 0x2b (freq of ==> 100KHz */
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/* see spec for more details about the calculation of this value) */
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mov r6, #(9 << 3 | 3)
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MV_REG_WRITE_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
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/* Enable the I2C master */
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/* Enable TWSI interrupt in main mask reg */
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mov r6, #0xC4
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MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
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/* Let the slow TWSI machine get used to the idea that it is enabled */
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bl _twsiDelay
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mov PC, r9 /* r9 is saved link register */
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/*******************************************************************************
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* _twsiDelay - Perform delay.
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*
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* DESCRIPTION:
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* The function performs a delay to enable TWSI logic to stable.
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*
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* INPUT:
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* None.
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*
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* OUTPUT:
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* None.
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*
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* RETURN:
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* None.
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*
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*******************************************************************************/
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_twsiDelay:
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mov r10, #0x100000 /*was 0x400*/
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_twsiDelayLoop:
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subs r10, r10, #1
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bne _twsiDelayLoop
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mov PC, LR
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/*******************************************************************************
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* _i2cRead - Read byte from I2C EEPROM device.
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*
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* DESCRIPTION:
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* The function returns a byte from I2C EEPROM device.
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* The EEPROM device is 7-bit address type.
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*
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* INPUT:
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* r4 has the DIMM0 base address with shift 1 bit to the left
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* r7 has the EEPROM offset
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*
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* OUTPUT:
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* None.
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*
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* RETURN:
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* r4 returns '0' if address can not be read.
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* r7 has byte value in case read is successful.
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*
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*******************************************************************************/
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_i2cRead:
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mov r9, LR /* Save link register */
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/* Transmit the device address and desired offset within the EEPROM. */
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/* Generate Start Bit */
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MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
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orr r6, r6, #TWSI_CONTROL_START_BIT
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MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
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/* Wait for the interrupt flag (bit3) to be set */
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mov r10, #0x50000
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loop_1:
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subs r10, r10, #1
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beq loop_1_timeout
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#ifdef MV78XX0
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MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH))
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tst r6, #BIT2
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#else
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MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG)
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tst r6, #BIT5
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#endif
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beq loop_1
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loop_1_timeout:
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/* Wait for the start bit to be reset by HW */
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mov r10, #0x50000
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loop_2:
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subs r10, r10, #1
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beq loop_2_timeout
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MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
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tst r6, #TWSI_CONTROL_START_BIT
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bne loop_2
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loop_2_timeout:
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/* Wait for the status TWSI_START_CONDITION_TRA = 0x8 */
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mov r10, #0x50000
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loop_3:
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subs r10, r10, #1
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beq loop_3_timeout
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MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
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cmp r6, #0x08
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bne loop_3
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loop_3_timeout:
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/* writing the address of (DIMM0/1 << 1) with write indication */
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mov r6, r4, LSL #1 /* Write operation address bit 0 must be 0 */
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MV_REG_WRITE_ASM (r6, r1, TWSI_DATA_REG(I2C_CH))
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bl _twsiDelay
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/* Clear the interrupt flag */
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MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
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bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET
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MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
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bl _twsiDelay
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/* Waiting for the interrupt flag to be set which means that the
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address has been transmitted */
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loop_4:
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#ifdef MV78XX0
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MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH))
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tst r6, #BIT2
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#else
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MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG)
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tst r6, #BIT5
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#endif
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beq loop_4 /* if tst = 0, then the bit is not set yet */
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/* Wait for status TWSI_ADDR_PLUS_WRITE_BIT_TRA_ACK_REC = 0x18 */
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mov r10, #0x50000 /* Set r10 to 0x50000 =~ 328,000 */
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loop_5:
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subs r10, r10, #1 /* timeout count down */
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bne testStatus
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mov r4, #0 /* r4 = 0 -> operation failed */
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b exit_i2cRead /* Exit if timeout (No DIMM) */
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testStatus:
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MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
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cmp r6, #0x18
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bne loop_5
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/* check if the offset is bigger than 256 byte*/
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tst r7, #0x80000000
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bne great_than_256
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/* Write the offset to be read from the DIMM EEPROM */
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MV_REG_WRITE_ASM (r7, r1, TWSI_DATA_REG(I2C_CH))
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b after_offset
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great_than_256:
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mov r10, r7, LSR #8
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and r10, r10, #0xff
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/* Write the offset0 to be read from the EEPROM */
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MV_REG_WRITE_ASM (r10, r1, TWSI_DATA_REG(I2C_CH))
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/* Clear the interrupt flag ==> signaling that the address can now
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be transmited */
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bl _twsiDelay
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MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
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bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET
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MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
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bl _twsiDelay
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/* Wait for the interrupt to be set again ==> address has transmited */
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loop_6_1:
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#ifdef MV78XX0
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MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH))
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tst r6, #BIT2
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#else
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MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG)
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tst r6, #BIT5
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#endif
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beq loop_6_1
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/* Wait for status TWSI_MAS_TRAN_DATA_BYTE_ACK_REC = 0x28 */
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loop_7_1:
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MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
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cmp r6, #0x28
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bne loop_7_1
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mov r10, r7
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and r10, r10, #0xff
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/* Write the offset1 to be read from the EEPROM */
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MV_REG_WRITE_ASM (r10, r1, TWSI_DATA_REG(I2C_CH))
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after_offset:
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/* Clear the interrupt flag ==> signaling that the address can now
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be transmited */
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bl _twsiDelay
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MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
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bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET
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MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
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bl _twsiDelay
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/* Wait for the interrupt to be set again ==> address has transmited */
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loop_6:
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#ifdef MV78XX0
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MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH))
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tst r6, #BIT2
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#else
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MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG)
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tst r6, #BIT5
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#endif
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beq loop_6
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/* Wait for status TWSI_MAS_TRAN_DATA_BYTE_ACK_REC = 0x28 */
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loop_7:
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MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
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cmp r6, #0x28
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bne loop_7
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/* Retransmit the device address with read indication to get the data */
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||
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/* generate a repeated start bit */
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MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
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orr r6, r6, #TWSI_CONTROL_START_BIT
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MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
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/* Clear the interrupt flag ==> the start bit will be transmitted. */
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bl _twsiDelay
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MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
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bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET
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MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
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bl _twsiDelay
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/* Wait for the interrupt flag (bit3) to be set */
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||
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loop_9:
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#ifdef MV78XX0
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||
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MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH))
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||
|
|
tst r6, #BIT2
|
||
|
|
#else
|
||
|
|
MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG)
|
||
|
|
tst r6, #BIT5
|
||
|
|
#endif
|
||
|
|
beq loop_9
|
||
|
|
|
||
|
|
/* Wait for the start bit to be reset by HW */
|
||
|
|
loop_8:
|
||
|
|
MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||
|
|
tst r6, #TWSI_CONTROL_START_BIT
|
||
|
|
bne loop_8
|
||
|
|
|
||
|
|
/* Wait for status TWSI_REPEATED_START_CONDITION_TRA = 0x10 */
|
||
|
|
loop_10:
|
||
|
|
MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
|
||
|
|
cmp r6, #0x10
|
||
|
|
bne loop_10
|
||
|
|
|
||
|
|
/* Writing the address of (DIMM0<<1) with read indication (bit0 is 1) */
|
||
|
|
mov r6, r4, LSL #1
|
||
|
|
orr r6, r6, #1 /* Read operation address bit 0 must be 1 */
|
||
|
|
MV_REG_WRITE_ASM (r6, r1, TWSI_DATA_REG(I2C_CH))
|
||
|
|
|
||
|
|
/* Clear the interrupt flag ==> the address will be transmitted */
|
||
|
|
bl _twsiDelay
|
||
|
|
MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||
|
|
bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET
|
||
|
|
MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||
|
|
bl _twsiDelay
|
||
|
|
|
||
|
|
/* Wait for the interrupt flag (bit3) to be set as a result of
|
||
|
|
transmitting the address. */
|
||
|
|
loop_11:
|
||
|
|
#ifdef MV78XX0
|
||
|
|
MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH))
|
||
|
|
tst r6, #BIT2
|
||
|
|
#else
|
||
|
|
MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG)
|
||
|
|
tst r6, #BIT5
|
||
|
|
#endif
|
||
|
|
beq loop_11
|
||
|
|
|
||
|
|
/* Wait for status TWSI_ADDR_PLUS_READ_BIT_TRA_ACK_REC = 0x40 */
|
||
|
|
loop_12:
|
||
|
|
MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
|
||
|
|
cmp r6, #0x40
|
||
|
|
bne loop_12
|
||
|
|
|
||
|
|
/* Clear the interrupt flag and the Acknoledge bit */
|
||
|
|
bl _twsiDelay
|
||
|
|
MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||
|
|
bic r6, r6, #(TWSI_CONTROL_INT_FLAG_SET | TWSI_CONTROL_ACK)
|
||
|
|
MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||
|
|
bl _twsiDelay
|
||
|
|
|
||
|
|
/* Wait for the interrupt flag (bit3) to be set */
|
||
|
|
loop_14:
|
||
|
|
#ifdef MV78XX0
|
||
|
|
MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH))
|
||
|
|
tst r6, #BIT2
|
||
|
|
#else
|
||
|
|
MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG)
|
||
|
|
tst r6, #BIT5
|
||
|
|
#endif
|
||
|
|
beq loop_14
|
||
|
|
|
||
|
|
/* Wait for status TWSI_MAS_REC_READ_DATA_ACK_NOT_TRA = 0x58 */
|
||
|
|
loop_15:
|
||
|
|
MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
|
||
|
|
cmp r6, #0x58
|
||
|
|
bne loop_15
|
||
|
|
|
||
|
|
/* Store the data in r7. */
|
||
|
|
MV_REG_READ_ASM (r7, r1, TWSI_DATA_REG(I2C_CH))
|
||
|
|
|
||
|
|
/* Generate stop bit */
|
||
|
|
MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||
|
|
orr r6, r6, #TWSI_CONTROL_STOP_BIT
|
||
|
|
MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||
|
|
|
||
|
|
|
||
|
|
/* Clear the interrupt flag */
|
||
|
|
bl _twsiDelay
|
||
|
|
MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||
|
|
bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET
|
||
|
|
MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||
|
|
bl _twsiDelay
|
||
|
|
|
||
|
|
/* Wait for the stop bit to be reset by HW */
|
||
|
|
loop_16:
|
||
|
|
MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
|
||
|
|
tst r6, #TWSI_CONTROL_INT_FLAG_SET
|
||
|
|
bne loop_16
|
||
|
|
|
||
|
|
exit_i2cRead:
|
||
|
|
mov PC, r9 /* r9 is saved link register */
|