377 lines
8.9 KiB
C
377 lines
8.9 KiB
C
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/*
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* (C) Copyright 2001-2003
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <command.h>
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#include <malloc.h>
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/* ------------------------------------------------------------------------- */
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#if 0
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#define FPGA_DEBUG
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#endif
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extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
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extern void lxt971_no_sleep(void);
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/* fpga configuration data - gzip compressed and generated by bin2c */
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const unsigned char fpgadata[] =
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{
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#include "fpgadata.c"
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};
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/*
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* include common fpga code (for esd boards)
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*/
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#include "../common/fpga.c"
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/* Prototypes */
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int gunzip(void *, int, unsigned char *, unsigned long *);
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#ifdef CONFIG_LCD_USED
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/* logo bitmap data - gzip compressed and generated by bin2c */
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unsigned char logo_bmp[] =
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{
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#include CFG_LCD_LOGO_NAME
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};
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/*
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* include common lcd code (for esd boards)
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*/
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#include "../common/lcd.c"
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#include CFG_LCD_HEADER_NAME
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#endif /* CONFIG_LCD_USED */
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int board_revision(void)
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{
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unsigned long cntrl0Reg;
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unsigned long value;
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/*
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* Get version of APC405 board from GPIO's
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*/
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/*
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* Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
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*/
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cntrl0Reg = mfdcr(cntrl0);
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mtdcr(cntrl0, cntrl0Reg | 0x03000000);
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out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000);
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out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000);
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udelay(1000); /* wait some time before reading input */
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value = in32(GPIO0_IR) & 0x00180000; /* get config bits */
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/*
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* Restore GPIO settings
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*/
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mtdcr(cntrl0, cntrl0Reg);
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switch (value) {
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case 0x00180000:
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/* CS2==1 && CS3==1 -> version <= 1.2 */
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return 2;
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case 0x00080000:
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/* CS2==0 && CS3==1 -> version 1.3 */
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return 3;
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#if 0 /* not yet manufactured ! */
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case 0x00100000:
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/* CS2==1 && CS3==0 -> version 1.4 */
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return 4;
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case 0x00000000:
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/* CS2==0 && CS3==0 -> version 1.5 */
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return 5;
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#endif
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default:
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/* should not be reached! */
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return 0;
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}
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}
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int board_early_init_f (void)
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{
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/*
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* First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
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*/
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out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
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out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
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out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */
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out32(GPIO0_OR, 0); /* pull prg low */
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/*
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* IRQ 0-15 405GP internally generated; active high; level sensitive
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* IRQ 16 405GP internally generated; active low; level sensitive
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* IRQ 17-24 RESERVED
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* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
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* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
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* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
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* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
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* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
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* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
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* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
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*/
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr(uicer, 0x00000000); /* disable all ints */
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mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
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mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
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mtdcr(uictr, 0x10000000); /* set int trigger levels */
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mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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/*
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* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
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*/
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#if 1 /* test-only */
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mtebc (epcr, 0xa8400000); /* ebc always driven */
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#else
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mtebc (epcr, 0x28400000); /* ebc in high-z */
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#endif
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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int misc_init_f (void)
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{
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return 0; /* dummy implementation */
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}
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int misc_init_r (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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volatile unsigned short *fpga_mode =
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(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
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volatile unsigned short *fpga_ctrl2 =
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(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL2);
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volatile unsigned char *duart0_mcr =
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(unsigned char *)((ulong)DUART0_BA + 4);
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volatile unsigned char *duart1_mcr =
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(unsigned char *)((ulong)DUART1_BA + 4);
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volatile unsigned short *fuji_lcdbl_pwm =
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(unsigned short *)((ulong)0xf0100200 + 0xa0);
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unsigned char *dst;
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ulong len = sizeof(fpgadata);
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int status;
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int index;
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int i;
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unsigned long cntrl0Reg;
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/*
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* Setup GPIO pins (CS6+CS7 as GPIO)
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*/
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cntrl0Reg = mfdcr(cntrl0);
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mtdcr(cntrl0, cntrl0Reg | 0x00300000);
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dst = malloc(CFG_FPGA_MAX_SIZE);
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if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
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printf ("GUNZIP ERROR - must RESET board to recover\n");
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do_reset (NULL, 0, 0, NULL);
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}
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status = fpga_boot(dst, len);
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if (status != 0) {
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printf("\nFPGA: Booting failed ");
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switch (status) {
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case ERROR_FPGA_PRG_INIT_LOW:
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printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_INIT_HIGH:
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printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_DONE:
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printf("(Timeout: DONE not high after programming FPGA)\n ");
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break;
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}
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/* display infos on fpgaimage */
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index = 15;
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for (i=0; i<4; i++) {
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len = dst[index];
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printf("FPGA: %s\n", &(dst[index+1]));
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index += len+3;
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}
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putc ('\n');
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/* delayed reboot */
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for (i=20; i>0; i--) {
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printf("Rebooting in %2d seconds \r",i);
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for (index=0;index<1000;index++)
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udelay(1000);
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}
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putc ('\n');
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do_reset(NULL, 0, 0, NULL);
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}
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/* restore gpio/cs settings */
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mtdcr(cntrl0, cntrl0Reg);
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puts("FPGA: ");
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/* display infos on fpgaimage */
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index = 15;
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for (i=0; i<4; i++) {
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len = dst[index];
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printf("%s ", &(dst[index+1]));
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index += len+3;
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}
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putc ('\n');
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free(dst);
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/*
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* Reset FPGA via FPGA_DATA pin
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*/
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SET_FPGA(FPGA_PRG | FPGA_CLK);
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udelay(1000); /* wait 1ms */
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SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
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udelay(1000); /* wait 1ms */
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/*
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* Write board revision in FPGA
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*/
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*fpga_ctrl2 = (*fpga_ctrl2 & 0xfff0) | (gd->board_type & 0x000f);
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/*
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* Enable power on PS/2 interface (with reset)
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*/
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*fpga_mode |= CFG_FPGA_CTRL_PS2_RESET;
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for (i=0;i<100;i++)
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udelay(1000);
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udelay(1000);
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*fpga_mode &= ~CFG_FPGA_CTRL_PS2_RESET;
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/*
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* Enable interrupts in exar duart mcr[3]
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*/
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*duart0_mcr = 0x08;
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*duart1_mcr = 0x08;
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/*
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* Init lcd interface and display logo
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*/
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lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
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regs_13806_640_480_16bpp,
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sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
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logo_bmp, sizeof(logo_bmp));
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/*
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* Reset microcontroller and setup backlight PWM controller
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*/
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*fpga_mode |= 0x0014;
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for (i=0;i<10;i++)
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udelay(1000);
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*fpga_mode |= 0x001c;
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*fuji_lcdbl_pwm = 0x00ff;
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return (0);
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}
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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unsigned char str[64];
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int i = getenv_r ("serial#", str, sizeof(str));
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puts ("Board: ");
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if (i == -1) {
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puts ("### No HW ID - assuming APC405");
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} else {
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puts(str);
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}
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gd->board_type = board_revision();
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printf(", Rev 1.%ld\n", gd->board_type);
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/*
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* Disable sleep mode in LXT971
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*/
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lxt971_no_sleep();
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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long int initdram (int board_type)
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{
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unsigned long val;
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mtdcr(memcfga, mem_mb0cf);
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val = mfdcr(memcfgd);
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#if 0
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printf("\nmb0cf=%x\n", val); /* test-only */
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printf("strap=%x\n", mfdcr(strap)); /* test-only */
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#endif
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return (4*1024*1024 << ((val & 0x000e0000) >> 17));
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}
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/* ------------------------------------------------------------------------- */
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int testdram (void)
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{
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/* TODO: XXX XXX XXX */
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printf ("test: 16 MB - ok\n");
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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#ifdef CONFIG_IDE_RESET
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void ide_set_reset(int on)
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{
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volatile unsigned short *fpga_mode =
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(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
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/*
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* Assert or deassert CompactFlash Reset Pin
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*/
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if (on) { /* assert RESET */
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*fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
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} else { /* release RESET */
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*fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
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}
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}
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#endif /* CONFIG_IDE_RESET */
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/* ------------------------------------------------------------------------- */
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