461 lines
17 KiB
C
461 lines
17 KiB
C
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/*
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* (C) Copyright 2003,Motorola Inc.
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* Xianghua Xiao, (X.Xiao@motorola.com)
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*
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* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
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*
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* (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
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* Added support for Wind River SBC8560 board
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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extern long int spd_sdram (void);
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/immap_85xx.h>
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#include <ioports.h>
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#include <spd.h>
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#include <miiphy.h>
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long int fixed_sdram (void);
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/*
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* I/O Port configuration table
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*
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* if conf is 1, then that port pin will be configured at boot time
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* according to the five values podr/pdir/ppar/psor/pdat for that entry
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*/
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const iop_conf_t iop_conf_tab[4][32] = {
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/* Port A configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
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/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
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/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
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/* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
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/* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
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/* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
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/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
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/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
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/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
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/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
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/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
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/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
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/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
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/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
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/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
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/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
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/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
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/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
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/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
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/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
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/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
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/* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
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/* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
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/* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
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/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
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/* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
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/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
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/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
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/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
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/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
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/* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
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/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
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},
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/* Port B configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
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/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
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/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
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/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
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/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
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/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
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/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
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/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
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/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
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/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
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/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
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/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
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/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
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/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
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/* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
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/* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
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/* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
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/* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
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/* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
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/* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
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/* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
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},
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/* Port C */
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{ /* conf ppar psor pdir podr pdat */
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/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
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/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
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/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
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/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
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/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
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/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
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/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
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/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
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/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
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/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
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/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
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/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
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/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
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/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
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/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
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/* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
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/* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
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/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
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/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
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/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
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/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
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/* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
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/* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
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/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
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/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
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/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
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/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
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/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
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/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
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/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
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/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
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/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
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},
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/* Port D */
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{ /* conf ppar psor pdir podr pdat */
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/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
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/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
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/* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 RTS */
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/* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */
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/* PD27 */ { 1, 1, 1, 1, 0, 0 }, /* SCC2 TxD */
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/* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 RTS */
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/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
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/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
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/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
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/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
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/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
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/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
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/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
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/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
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/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
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/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
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/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
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/* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
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/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
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/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
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/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
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/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
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/* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
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/* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
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/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
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/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
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/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
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/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
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/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
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}
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};
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int board_early_init_f (void)
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{
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#if defined(CONFIG_PCI)
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volatile immap_t *immr = (immap_t *)CFG_IMMR;
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volatile ccsr_pcix_t *pci = &immr->im_pcix;
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pci->peer &= 0xfffffffdf; /* disable master abort */
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#endif
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return 0;
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}
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void reset_phy (void)
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{
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#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
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volatile unsigned char *bcsr = (unsigned char *) CFG_BCSR;
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#endif
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/* reset Giga bit Ethernet port if needed here */
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/* reset the CPM FEC port */
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#if (CONFIG_ETHER_INDEX == 2)
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bcsr[0] &= ~0x20;
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udelay(2);
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bcsr[0] |= 0x20;
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udelay(1000);
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#elif (CONFIG_ETHER_INDEX == 3)
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bcsr[0] &= ~0x10;
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udelay(2);
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bcsr[0] |= 0x10;
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udelay(1000);
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#endif
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#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
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/* reset PHY */
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miiphy_reset("FCC1 ETHERNET", 0x0);
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/* change PHY address to 0x02 */
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bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
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bb_miiphy_write(NULL, 0x02, PHY_BMCR,
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PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
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#endif /* CONFIG_MII */
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}
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int checkboard (void)
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{
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sys_info_t sysinfo;
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get_sys_info (&sysinfo);
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#ifdef CONFIG_SBC8560
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printf ("Board: Wind River SBC8560 Board\n");
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#else
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printf ("Board: Wind River SBC8540 Board\n");
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#endif
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printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
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printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
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printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
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if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
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|| (CFG_LBC_LCRR & 0x0f) == 8) {
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printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f));
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} else {
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printf("\tLBC: unknown\n");
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}
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printf("\tCPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
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printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
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return (0);
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}
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long int initdram (int board_type)
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{
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long dram_size = 0;
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extern long spd_sdram (void);
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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#if 0
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#if !defined(CONFIG_RAM_AS_FLASH)
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volatile ccsr_lbc_t *lbc= &immap->im_lbc;
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sys_info_t sysinfo;
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uint temp_lbcdll = 0;
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#endif
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#endif /* 0 */
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#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
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volatile ccsr_gur_t *gur= &immap->im_gur;
|
||
|
|
#endif
|
||
|
|
#if defined(CONFIG_DDR_DLL)
|
||
|
|
uint temp_ddrdll = 0;
|
||
|
|
|
||
|
|
/* Work around to stabilize DDR DLL */
|
||
|
|
temp_ddrdll = gur->ddrdllcr;
|
||
|
|
gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
|
||
|
|
asm("sync;isync;msync");
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if defined(CONFIG_SPD_EEPROM)
|
||
|
|
dram_size = spd_sdram ();
|
||
|
|
#else
|
||
|
|
dram_size = fixed_sdram ();
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if 0
|
||
|
|
#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */
|
||
|
|
get_sys_info(&sysinfo);
|
||
|
|
/* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
|
||
|
|
if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
|
||
|
|
lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
|
||
|
|
} else {
|
||
|
|
#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
|
||
|
|
lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */
|
||
|
|
#endif
|
||
|
|
lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
|
||
|
|
udelay(200);
|
||
|
|
temp_lbcdll = gur->lbcdllcr;
|
||
|
|
gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
|
||
|
|
asm("sync;isync;msync");
|
||
|
|
}
|
||
|
|
lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
|
||
|
|
lbc->br2 = CFG_BR2_PRELIM;
|
||
|
|
lbc->lbcr = CFG_LBC_LBCR;
|
||
|
|
lbc->lsdmr = CFG_LBC_LSDMR_1;
|
||
|
|
asm("sync");
|
||
|
|
(unsigned int) * (ulong *)0 = 0x000000ff;
|
||
|
|
lbc->lsdmr = CFG_LBC_LSDMR_2;
|
||
|
|
asm("sync");
|
||
|
|
(unsigned int) * (ulong *)0 = 0x000000ff;
|
||
|
|
lbc->lsdmr = CFG_LBC_LSDMR_3;
|
||
|
|
asm("sync");
|
||
|
|
(unsigned int) * (ulong *)0 = 0x000000ff;
|
||
|
|
lbc->lsdmr = CFG_LBC_LSDMR_4;
|
||
|
|
asm("sync");
|
||
|
|
(unsigned int) * (ulong *)0 = 0x000000ff;
|
||
|
|
lbc->lsdmr = CFG_LBC_LSDMR_5;
|
||
|
|
asm("sync");
|
||
|
|
lbc->lsrt = CFG_LBC_LSRT;
|
||
|
|
asm("sync");
|
||
|
|
lbc->mrtpr = CFG_LBC_MRTPR;
|
||
|
|
asm("sync");
|
||
|
|
#endif
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if defined(CONFIG_DDR_ECC)
|
||
|
|
{
|
||
|
|
/* Initialize all of memory for ECC, then
|
||
|
|
* enable errors */
|
||
|
|
uint *p = 0;
|
||
|
|
uint i = 0;
|
||
|
|
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
||
|
|
volatile ccsr_ddr_t *ddr= &immap->im_ddr;
|
||
|
|
dma_init();
|
||
|
|
for (*p = 0; p < (uint *)(8 * 1024); p++) {
|
||
|
|
if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
|
||
|
|
*p = (unsigned int)0xdeadbeef;
|
||
|
|
if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
|
||
|
|
}
|
||
|
|
|
||
|
|
/* 8K */
|
||
|
|
dma_xfer((uint *)0x2000,0x2000,(uint *)0);
|
||
|
|
/* 16K */
|
||
|
|
dma_xfer((uint *)0x4000,0x4000,(uint *)0);
|
||
|
|
/* 32K */
|
||
|
|
dma_xfer((uint *)0x8000,0x8000,(uint *)0);
|
||
|
|
/* 64K */
|
||
|
|
dma_xfer((uint *)0x10000,0x10000,(uint *)0);
|
||
|
|
/* 128k */
|
||
|
|
dma_xfer((uint *)0x20000,0x20000,(uint *)0);
|
||
|
|
/* 256k */
|
||
|
|
dma_xfer((uint *)0x40000,0x40000,(uint *)0);
|
||
|
|
/* 512k */
|
||
|
|
dma_xfer((uint *)0x80000,0x80000,(uint *)0);
|
||
|
|
/* 1M */
|
||
|
|
dma_xfer((uint *)0x100000,0x100000,(uint *)0);
|
||
|
|
/* 2M */
|
||
|
|
dma_xfer((uint *)0x200000,0x200000,(uint *)0);
|
||
|
|
/* 4M */
|
||
|
|
dma_xfer((uint *)0x400000,0x400000,(uint *)0);
|
||
|
|
|
||
|
|
for (i = 1; i < dram_size / 0x800000; i++) {
|
||
|
|
dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Enable errors for ECC */
|
||
|
|
ddr->err_disable = 0x00000000;
|
||
|
|
asm("sync;isync;msync");
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
return dram_size;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
#if defined(CFG_DRAM_TEST)
|
||
|
|
int testdram (void)
|
||
|
|
{
|
||
|
|
uint *pstart = (uint *) CFG_MEMTEST_START;
|
||
|
|
uint *pend = (uint *) CFG_MEMTEST_END;
|
||
|
|
uint *p;
|
||
|
|
|
||
|
|
printf("SDRAM test phase 1:\n");
|
||
|
|
for (p = pstart; p < pend; p++)
|
||
|
|
*p = 0xaaaaaaaa;
|
||
|
|
|
||
|
|
for (p = pstart; p < pend; p++) {
|
||
|
|
if (*p != 0xaaaaaaaa) {
|
||
|
|
printf ("SDRAM test fails at: %08x\n", (uint) p);
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
printf("SDRAM test phase 2:\n");
|
||
|
|
for (p = pstart; p < pend; p++)
|
||
|
|
*p = 0x55555555;
|
||
|
|
|
||
|
|
for (p = pstart; p < pend; p++) {
|
||
|
|
if (*p != 0x55555555) {
|
||
|
|
printf ("SDRAM test fails at: %08x\n", (uint) p);
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
printf("SDRAM test passed.\n");
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if !defined(CONFIG_SPD_EEPROM)
|
||
|
|
/*************************************************************************
|
||
|
|
* fixed sdram init -- doesn't use serial presence detect.
|
||
|
|
************************************************************************/
|
||
|
|
long int fixed_sdram (void)
|
||
|
|
{
|
||
|
|
|
||
|
|
#define CFG_DDR_CONTROL 0xc2000000
|
||
|
|
|
||
|
|
#ifndef CFG_RAMBOOT
|
||
|
|
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
||
|
|
volatile ccsr_ddr_t *ddr= &immap->im_ddr;
|
||
|
|
|
||
|
|
ddr->cs0_bnds = 0x00000007;
|
||
|
|
ddr->cs1_bnds = 0x0010001f;
|
||
|
|
ddr->cs2_bnds = 0x00000000;
|
||
|
|
ddr->cs3_bnds = 0x00000000;
|
||
|
|
ddr->cs0_config = 0x80000102;
|
||
|
|
ddr->cs1_config = 0x80000102;
|
||
|
|
ddr->cs2_config = 0x00000000;
|
||
|
|
ddr->cs3_config = 0x00000000;
|
||
|
|
ddr->timing_cfg_1 = 0x37334321;
|
||
|
|
ddr->timing_cfg_2 = 0x00000800;
|
||
|
|
ddr->sdram_cfg = 0x42000000;
|
||
|
|
ddr->sdram_mode = 0x00000022;
|
||
|
|
ddr->sdram_interval = 0x05200100;
|
||
|
|
ddr->err_sbe = 0x00ff0000;
|
||
|
|
#if defined (CONFIG_DDR_ECC)
|
||
|
|
ddr->err_disable = 0x0000000D;
|
||
|
|
#endif
|
||
|
|
asm("sync;isync;msync");
|
||
|
|
udelay(500);
|
||
|
|
#if defined (CONFIG_DDR_ECC)
|
||
|
|
/* Enable ECC checking */
|
||
|
|
ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
|
||
|
|
#else
|
||
|
|
ddr->sdram_cfg = CFG_DDR_CONTROL;
|
||
|
|
#endif
|
||
|
|
asm("sync; isync; msync");
|
||
|
|
udelay(500);
|
||
|
|
#endif
|
||
|
|
return CFG_SDRAM_SIZE * 1024 * 1024;
|
||
|
|
}
|
||
|
|
#endif /* !defined(CONFIG_SPD_EEPROM) */
|