365 lines
8.2 KiB
C
365 lines
8.2 KiB
C
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/*
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* (C) Copyright 2002
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* Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <linux/ctype.h>
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#include <common.h>
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#include "fpga.h"
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int power_on_reset(void);
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/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
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static int fpga_get_version(fpga_t* fpga, char* name)
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{
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char vname[12];
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/*
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* Net-list string format:
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* "vvvvvvvvddddddddn...".
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* Version Date Name
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* "0000000322042002PUMA" = PUMA version 3 from 22.04.2002.
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*/
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if (strlen(name) < (16 + strlen(fpga->name)))
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goto failure;
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/* Check FPGA name */
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if (strcmp(&name[16], fpga->name) != 0)
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goto failure;
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/* Get version number */
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memcpy(vname, name, 8);
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vname[8] = '\0';
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return simple_strtoul(vname, NULL, 16);
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failure:
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printf("Image name %s is invalid\n", name);
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return -1;
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}
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/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
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static fpga_t* fpga_get(char* fpga_name)
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{
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char name[FPGA_NAME_LEN];
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int i;
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if (strlen(fpga_name) >= FPGA_NAME_LEN)
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goto failure;
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for (i = 0; i < strlen(fpga_name); i++)
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name[i] = toupper(fpga_name[i]);
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name[i] = '\0';
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for (i = 0; i < fpga_count; i++) {
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if (strcmp(name, fpga_list[i].name) == 0)
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return &fpga_list[i];
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}
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failure:
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printf("FPGA: name %s is invalid\n", fpga_name);
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return NULL;
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}
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/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
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static void fpga_status (fpga_t* fpga)
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{
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/* Check state */
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if (fpga_control(fpga, FPGA_DONE_IS_HIGH))
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printf ("%s is loaded (%08lx)\n",
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fpga->name, fpga_control(fpga, FPGA_GET_ID));
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else
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printf ("%s is NOT loaded\n", fpga->name);
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}
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/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
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#define FPGA_RESET_TIMEOUT 100 /* = 10 ms */
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static int fpga_reset (fpga_t* fpga)
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{
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int i;
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/* Set PROG to low and wait til INIT goes low */
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fpga_control(fpga, FPGA_PROG_SET_LOW);
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for (i = 0; i < FPGA_RESET_TIMEOUT; i++) {
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udelay (100);
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if (!fpga_control(fpga, FPGA_INIT_IS_HIGH))
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break;
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}
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if (i == FPGA_RESET_TIMEOUT)
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goto failure;
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/* Set PROG to high and wait til INIT goes high */
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fpga_control(fpga, FPGA_PROG_SET_HIGH);
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for (i = 0; i < FPGA_RESET_TIMEOUT; i++) {
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udelay (100);
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if (fpga_control(fpga, FPGA_INIT_IS_HIGH))
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break;
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}
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if (i == FPGA_RESET_TIMEOUT)
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goto failure;
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return 0;
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failure:
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return 1;
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}
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/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
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#define FPGA_LOAD_TIMEOUT 100 /* = 10 ms */
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static int fpga_load (fpga_t* fpga, ulong addr, int checkall)
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{
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volatile uchar *fpga_addr = (volatile uchar *)fpga->conf_base;
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image_header_t hdr;
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ulong len, checksum;
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uchar *data = (uchar *)&hdr;
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char *s, msg[32];
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int verify, i;
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/*
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* Check the image header and data of the net-list
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*/
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memcpy (&hdr, (char *)addr, sizeof(image_header_t));
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if (hdr.ih_magic != IH_MAGIC) {
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strcpy (msg, "Bad Image Magic Number");
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goto failure;
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}
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len = sizeof(image_header_t);
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checksum = hdr.ih_hcrc;
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hdr.ih_hcrc = 0;
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if (crc32 (0, data, len) != checksum) {
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strcpy (msg, "Bad Image Header CRC");
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goto failure;
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}
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data = (uchar*)(addr + sizeof(image_header_t));
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len = hdr.ih_size;
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s = getenv ("verify");
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verify = (s && (*s == 'n')) ? 0 : 1;
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if (verify) {
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if (crc32 (0, data, len) != hdr.ih_dcrc) {
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strcpy (msg, "Bad Image Data CRC");
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goto failure;
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}
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}
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if (checkall && fpga_get_version(fpga, (char *)(hdr.ih_name)) < 0)
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return 1;
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/* align length */
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if (len & 1)
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++len;
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/*
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* Reset FPGA and wait for completion
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*/
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if (fpga_reset(fpga)) {
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strcpy (msg, "Reset Timeout");
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goto failure;
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}
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printf ("(%s)... ", hdr.ih_name);
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/*
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* Copy data to FPGA
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*/
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fpga_control (fpga, FPGA_LOAD_MODE);
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while (len--) {
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*fpga_addr = *data++;
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}
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fpga_control (fpga, FPGA_READ_MODE);
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/*
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* Wait for completion and check error status if timeout
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*/
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for (i = 0; i < FPGA_LOAD_TIMEOUT; i++) {
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udelay (100);
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if (fpga_control (fpga, FPGA_DONE_IS_HIGH))
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break;
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}
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if (i == FPGA_LOAD_TIMEOUT) {
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if (fpga_control(fpga, FPGA_INIT_IS_HIGH))
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strcpy(msg, "Invalid Size");
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else
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strcpy(msg, "CRC Error");
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goto failure;
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}
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printf("done\n");
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return 0;
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failure:
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printf("ERROR: %s\n", msg);
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return 1;
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}
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#if (CONFIG_COMMANDS & CFG_CMD_BSP)
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/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
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int do_fpga (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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ulong addr = 0;
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int i;
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fpga_t* fpga;
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if (argc < 2)
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goto failure;
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if (strncmp(argv[1], "stat", 4) == 0) { /* status */
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if (argc == 2) {
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for (i = 0; i < fpga_count; i++) {
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fpga_status (&fpga_list[i]);
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}
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}
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else if (argc == 3) {
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if ((fpga = fpga_get(argv[2])) == 0)
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goto failure;
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fpga_status (fpga);
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}
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else
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goto failure;
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}
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else if (strcmp(argv[1],"load") == 0) { /* load */
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if (argc == 3 && fpga_count == 1) {
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fpga = &fpga_list[0];
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}
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else if (argc == 4) {
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if ((fpga = fpga_get(argv[2])) == 0)
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goto failure;
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}
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else
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goto failure;
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addr = simple_strtoul(argv[argc-1], NULL, 16);
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printf ("FPGA load %s: addr %08lx: ",
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fpga->name, addr);
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fpga_load (fpga, addr, 1);
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}
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else if (strncmp(argv[1], "rese", 4) == 0) { /* reset */
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if (argc == 2 && fpga_count == 1) {
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fpga = &fpga_list[0];
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}
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else if (argc == 3) {
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if ((fpga = fpga_get(argv[2])) == 0)
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goto failure;
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}
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else
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goto failure;
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printf ("FPGA reset %s: ", fpga->name);
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if (fpga_reset(fpga))
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printf ("ERROR: Timeout\n");
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else
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printf ("done\n");
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}
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else
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goto failure;
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return 0;
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failure:
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printf ("Usage:\n%s\n", cmdtp->usage);
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return 1;
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}
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U_BOOT_CMD(
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fpga, 4, 1, do_fpga,
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"fpga - access FPGA(s)\n",
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"fpga status [name] - print FPGA status\n"
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"fpga reset [name] - reset FPGA\n"
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"fpga load [name] addr - load FPGA configuration data\n"
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);
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#endif /* CONFIG_COMMANDS & CFG_CMD_BSP */
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/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
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int fpga_init (void)
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{
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ulong addr;
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ulong new_id, old_id = 0;
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image_header_t *hdr;
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fpga_t* fpga;
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int do_load, i, j;
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char name[16], *s;
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/*
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* Port setup for FPGA control
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*/
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for (i = 0; i < fpga_count; i++) {
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fpga_control(&fpga_list[i], FPGA_INIT_PORTS);
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}
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/*
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* Load FPGA(s): a new net-list is loaded if the FPGA is
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* empty, Power-on-Reset or the old one is not up-to-date
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*/
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for (i = 0; i < fpga_count; i++) {
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fpga = &fpga_list[i];
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printf ("%s: ", fpga->name);
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for (j = 0; j < strlen(fpga->name); j++)
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name[j] = tolower(fpga->name[j]);
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name[j] = '\0';
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sprintf(name, "%s_addr", name);
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addr = 0;
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if ((s = getenv(name)) != NULL)
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addr = simple_strtoul(s, NULL, 16);
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if (!addr) {
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printf ("env. variable %s undefined\n", name);
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return 1;
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}
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hdr = (image_header_t *)addr;
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if ((new_id = fpga_get_version(fpga, (char *)(hdr->ih_name))) == -1)
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return 1;
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do_load = 1;
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if (!power_on_reset() && fpga_control(fpga, FPGA_DONE_IS_HIGH)) {
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old_id = fpga_control(fpga, FPGA_GET_ID);
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if (new_id == old_id)
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do_load = 0;
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}
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if (do_load) {
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printf ("loading ");
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fpga_load (fpga, addr, 0);
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} else {
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printf ("loaded (%08lx)\n", old_id);
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}
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}
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return 0;
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}
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