253 lines
6.8 KiB
C
253 lines
6.8 KiB
C
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/*
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* (C) Copyright 2003
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* Josef Baumgartner <josef.baumgartner@telex.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <watchdog.h>
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#ifdef CONFIG_M5272
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#include <asm/m5272.h>
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#include <asm/immap_5272.h>
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#endif
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#ifdef CONFIG_M5282
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#include <asm/m5282.h>
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#include <asm/immap_5282.h>
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#endif
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#ifdef CONFIG_M5249
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#include <asm/m5249.h>
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#endif
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#if defined(CONFIG_M5272)
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/*
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* Breath some life into the CPU...
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*
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* Set up the memory map,
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* initialize a bunch of registers,
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* initialize the UPM's
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*/
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void cpu_init_f (void)
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{
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/* if we come from RAM we assume the CPU is
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* already initialized.
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*/
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#ifndef CONFIG_MONITOR_IS_IN_RAM
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volatile immap_t *regp = (immap_t *)CFG_MBAR;
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volatile unsigned char *mbar;
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mbar = (volatile unsigned char *) CFG_MBAR;
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regp->sysctrl_reg.sc_scr = CFG_SCR;
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regp->sysctrl_reg.sc_spr = CFG_SPR;
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/* Setup Ports: */
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regp->gpio_reg.gpio_pacnt = CFG_PACNT;
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regp->gpio_reg.gpio_paddr = CFG_PADDR;
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regp->gpio_reg.gpio_padat = CFG_PADAT;
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regp->gpio_reg.gpio_pbcnt = CFG_PBCNT;
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regp->gpio_reg.gpio_pbddr = CFG_PBDDR;
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regp->gpio_reg.gpio_pbdat = CFG_PBDAT;
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regp->gpio_reg.gpio_pdcnt = CFG_PDCNT;
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/* Memory Controller: */
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regp->csctrl_reg.cs_br0 = CFG_BR0_PRELIM;
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regp->csctrl_reg.cs_or0 = CFG_OR0_PRELIM;
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#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
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regp->csctrl_reg.cs_br1 = CFG_BR1_PRELIM;
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regp->csctrl_reg.cs_or1 = CFG_OR1_PRELIM;
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#endif
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#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
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regp->csctrl_reg.cs_br2 = CFG_BR2_PRELIM;
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regp->csctrl_reg.cs_or2 = CFG_OR2_PRELIM;
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#endif
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#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
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regp->csctrl_reg.cs_br3 = CFG_BR3_PRELIM;
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regp->csctrl_reg.cs_or3 = CFG_OR3_PRELIM;
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#endif
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#if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM)
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regp->csctrl_reg.cs_br4 = CFG_BR4_PRELIM;
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regp->csctrl_reg.cs_or4 = CFG_OR4_PRELIM;
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#endif
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#if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM)
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regp->csctrl_reg.cs_br5 = CFG_BR5_PRELIM;
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regp->csctrl_reg.cs_or5 = CFG_OR5_PRELIM;
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#endif
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#if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM)
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regp->csctrl_reg.cs_br6 = CFG_BR6_PRELIM;
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regp->csctrl_reg.cs_or6 = CFG_OR6_PRELIM;
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#endif
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#if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM)
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regp->csctrl_reg.cs_br7 = CFG_BR7_PRELIM;
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regp->csctrl_reg.cs_or7 = CFG_OR7_PRELIM;
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#endif
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#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
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/* enable instruction cache now */
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icache_enable();
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}
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/*
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* initialize higher level parts of CPU like timers
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*/
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int cpu_init_r (void)
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{
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return (0);
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}
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#endif /* #if defined(CONFIG_M5272) */
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#ifdef CONFIG_M5282
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/*
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* Breath some life into the CPU...
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*
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* Set up the memory map,
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* initialize a bunch of registers,
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* initialize the UPM's
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*/
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void cpu_init_f (void)
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{
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}
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/*
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* initialize higher level parts of CPU like timers
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*/
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int cpu_init_r (void)
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{
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return (0);
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}
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#endif
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#if defined(CONFIG_M5249)
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/*
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* Breath some life into the CPU...
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*
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* Set up the memory map,
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* initialize a bunch of registers,
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* initialize the UPM's
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*/
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void cpu_init_f (void)
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{
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#ifndef CFG_PLL_BYPASS
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/*
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* Setup the PLL to run at the specified speed
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*
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*/
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volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
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unsigned long pllcr;
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#ifdef CFG_FAST_CLK
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pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */
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#else
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pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */
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#endif
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cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
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mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */
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mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */
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pllcr ^= 0x00000001; /* Set pll bypass to 1 */
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mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */
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udelay(0x20); /* Wait for a lock ... */
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#endif /* #ifndef CFG_PLL_BYPASS */
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/*
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* NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
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* (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
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* which is their primary function.
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* ~Jeremy
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*/
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mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_GPIO_FUNC);
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mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_GPIO1_FUNC);
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mbar2_writeLong(MCFSIM_GPIO_EN, CFG_GPIO_EN);
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mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_GPIO1_EN);
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mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_GPIO_OUT);
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mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_GPIO1_OUT);
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/*
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* dBug Compliance:
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* You can verify these values by using dBug's 'ird'
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* (Internal Register Display) command
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* ~Jeremy
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*
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*/
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mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */
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mbar_writeByte(MCFSIM_SYPCR, 0x00);
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mbar_writeByte(MCFSIM_SWIVR, 0x0f);
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mbar_writeByte(MCFSIM_SWSR, 0x00);
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mbar_writeLong(MCFSIM_IMR, 0xfffffbff);
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mbar_writeByte(MCFSIM_SWDICR, 0x00);
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mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
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mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
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mbar_writeByte(MCFSIM_I2CICR, 0x00);
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mbar_writeByte(MCFSIM_UART1ICR, 0x00);
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mbar_writeByte(MCFSIM_UART2ICR, 0x00);
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mbar_writeByte(MCFSIM_ICR6, 0x00);
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mbar_writeByte(MCFSIM_ICR7, 0x00);
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mbar_writeByte(MCFSIM_ICR8, 0x00);
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mbar_writeByte(MCFSIM_ICR9, 0x00);
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mbar_writeByte(MCFSIM_QSPIICR, 0x00);
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mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
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mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
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mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
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mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
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/* Setup interrupt priorities for gpio7 */
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/* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
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/* IDE Config registers */
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mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
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mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
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/*
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* Setup chip selects...
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*/
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mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1);
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mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1);
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mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1);
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mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0);
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mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
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mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);
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/* enable instruction cache now */
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icache_enable();
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}
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/*
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* initialize higher level parts of CPU like timers
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*/
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int cpu_init_r (void)
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{
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return (0);
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}
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#endif /* #if defined(CONFIG_M5249) */
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