237 lines
5.4 KiB
C
237 lines
5.4 KiB
C
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/*
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* (C) Copyright 2003 Motorola Inc.
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* Modified by Xianghua Xiao, X.Xiao@motorola.com
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <asm/processor.h>
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#include <ioports.h>
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#include <asm/io.h>
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#ifdef CONFIG_CPM2
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static void config_8560_ioports (volatile immap_t * immr)
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{
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int portnum;
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for (portnum = 0; portnum < 4; portnum++) {
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uint pmsk = 0,
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ppar = 0,
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psor = 0,
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pdir = 0,
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podr = 0,
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pdat = 0;
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iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
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iop_conf_t *eiopc = iopc + 32;
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uint msk = 1;
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/*
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* NOTE:
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* index 0 refers to pin 31,
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* index 31 refers to pin 0
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*/
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while (iopc < eiopc) {
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if (iopc->conf) {
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pmsk |= msk;
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if (iopc->ppar)
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ppar |= msk;
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if (iopc->psor)
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psor |= msk;
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if (iopc->pdir)
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pdir |= msk;
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if (iopc->podr)
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podr |= msk;
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if (iopc->pdat)
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pdat |= msk;
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}
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msk <<= 1;
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iopc++;
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}
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if (pmsk != 0) {
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volatile ioport_t *iop = ioport_addr (immr, portnum);
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uint tpmsk = ~pmsk;
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/*
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* the (somewhat confused) paragraph at the
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* bottom of page 35-5 warns that there might
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* be "unknown behaviour" when programming
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* PSORx and PDIRx, if PPARx = 1, so I
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* decided this meant I had to disable the
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* dedicated function first, and enable it
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* last.
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*/
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iop->ppar &= tpmsk;
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iop->psor = (iop->psor & tpmsk) | psor;
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iop->podr = (iop->podr & tpmsk) | podr;
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iop->pdat = (iop->pdat & tpmsk) | pdat;
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iop->pdir = (iop->pdir & tpmsk) | pdir;
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iop->ppar |= ppar;
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}
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}
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}
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#endif
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/*
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* Breathe some life into the CPU...
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*
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* Set up the memory map
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* initialize a bunch of registers
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*/
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void cpu_init_f (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile ccsr_lbc_t *memctl = &immap->im_lbc;
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extern void m8560_cpm_reset (void);
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/* Pointer is writable since we allocated a register for it */
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gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
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/* Clear initial global data */
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memset ((void *) gd, 0, sizeof (gd_t));
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#ifdef CONFIG_CPM2
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config_8560_ioports(immap);
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#endif
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/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
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* addresses - these have to be modified later when FLASH size
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* has been determined
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*/
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#if defined(CFG_OR0_REMAP)
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memctl->or0 = CFG_OR0_REMAP;
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#endif
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#if defined(CFG_OR1_REMAP)
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memctl->or1 = CFG_OR1_REMAP;
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#endif
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/* now restrict to preliminary range */
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#if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM)
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memctl->br0 = CFG_BR0_PRELIM;
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memctl->or0 = CFG_OR0_PRELIM;
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#endif
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#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
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memctl->or1 = CFG_OR1_PRELIM;
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memctl->br1 = CFG_BR1_PRELIM;
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#endif
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#if !defined(CONFIG_MPC85xx)
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#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
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memctl->or2 = CFG_OR2_PRELIM;
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memctl->br2 = CFG_BR2_PRELIM;
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#endif
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#endif
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#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
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memctl->or3 = CFG_OR3_PRELIM;
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memctl->br3 = CFG_BR3_PRELIM;
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#endif
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#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
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memctl->or4 = CFG_OR4_PRELIM;
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memctl->br4 = CFG_BR4_PRELIM;
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#endif
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#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
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memctl->or5 = CFG_OR5_PRELIM;
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memctl->br5 = CFG_BR5_PRELIM;
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#endif
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#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
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memctl->or6 = CFG_OR6_PRELIM;
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memctl->br6 = CFG_BR6_PRELIM;
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#endif
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#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
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memctl->or7 = CFG_OR7_PRELIM;
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memctl->br7 = CFG_BR7_PRELIM;
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#endif
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#if defined(CONFIG_CPM2)
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m8560_cpm_reset();
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#endif
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}
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/*
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* Initialize L2 as cache.
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*
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* The newer 8548, etc, parts have twice as much cache, but
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* use the same bit-encoding as the older 8555, etc, parts.
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*
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* FIXME: Use PVR_VER(pvr) == 1 test here instead of SVR_VER()?
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*/
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int cpu_init_r(void)
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{
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#if defined(CONFIG_L2_CACHE)
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache;
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volatile uint cache_ctl;
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uint svr, ver;
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svr = get_svr();
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ver = SVR_VER(svr);
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asm("msync;isync");
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cache_ctl = l2cache->l2ctl;
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switch (cache_ctl & 0x30000000) {
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case 0x20000000:
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if (ver == SVR_8548 || ver == SVR_8548_E) {
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printf ("L2 cache 512KB:");
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} else {
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printf ("L2 cache 256KB:");
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}
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break;
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case 0x00000000:
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case 0x10000000:
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case 0x30000000:
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default:
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printf ("L2 cache unknown size (0x%08x)\n", cache_ctl);
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return -1;
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}
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asm("msync;isync");
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l2cache->l2ctl = 0x68000000; /* invalidate */
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cache_ctl = l2cache->l2ctl;
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asm("msync;isync");
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l2cache->l2ctl = 0xa8000000; /* enable 256KB L2 cache */
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cache_ctl = l2cache->l2ctl;
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asm("msync;isync");
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printf(" enabled\n");
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#else
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printf("L2 cache: disabled\n");
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#endif
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return 0;
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}
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