153 lines
3.3 KiB
ArmAsm
153 lines
3.3 KiB
ArmAsm
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/*
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* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
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* Scott McNutt <smcnutt@psyent.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <asm/opcodes.h>
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.text
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.align 4
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.global _exception
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_exception:
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/* SAVE ALL REGS -- this allows trap and unimplemented
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* instruction handlers to be coded conveniently in C
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*/
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addi sp, sp, -(33*4)
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stw r0, 0(sp)
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stw r1, 4(sp)
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stw r2, 8(sp)
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stw r3, 12(sp)
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stw r4, 16(sp)
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stw r5, 20(sp)
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stw r6, 24(sp)
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stw r7, 28(sp)
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stw r8, 32(sp)
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stw r9, 36(sp)
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stw r10, 40(sp)
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stw r11, 44(sp)
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stw r12, 48(sp)
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stw r13, 52(sp)
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stw r14, 56(sp)
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stw r15, 60(sp)
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stw r16, 64(sp)
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stw r17, 68(sp)
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stw r19, 72(sp)
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stw r19, 76(sp)
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stw r20, 80(sp)
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stw r21, 84(sp)
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stw r22, 88(sp)
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stw r23, 92(sp)
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stw r24, 96(sp)
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stw r25, 100(sp)
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stw r26, 104(sp)
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stw r27, 108(sp)
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stw r28, 112(sp)
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stw r29, 116(sp)
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stw r30, 120(sp)
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stw r31, 124(sp)
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rdctl et, estatus
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stw et, 128(sp)
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/* If interrupts are disabled -- software interrupt */
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rdctl et, estatus
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andi et, et, 1
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beq et, r0, 0f
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/* If no interrupts are pending -- software interrupt */
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rdctl et, ipending
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beq et, r0, 0f
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/* HARDWARE INTERRUPT: Call interrupt handler */
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movhi r3, %hi(external_interrupt)
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ori r3, r3, %lo(external_interrupt)
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mov r4, sp /* ptr to regs */
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callr r3
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/* Return address fixup: execution resumes by re-issue of
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* interrupted instruction at ea-4 (ea == r29). Here we do
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* simple fixup to allow common exception return.
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*/
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ldw r3, 116(sp)
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addi r3, r3, -4
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stw r3, 116(sp)
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br _exception_return
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0:
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/* TRAP EXCEPTION */
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movhi r3, %hi(OPC_TRAP)
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ori r3, r3, %lo(OPC_TRAP)
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addi r1, ea, -4
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ldw r1, 0(r1)
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bne r1, r3, 1f
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movhi r3, %hi(trap_handler)
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ori r3, r3, %lo(trap_handler)
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mov r4, sp /* ptr to regs */
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callr r3
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br _exception_return
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1:
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/* UNIMPLEMENTED INSTRUCTION EXCEPTION */
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movhi r3, %hi(soft_emulation)
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ori r3, r3, %lo(soft_emulation)
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mov r4, sp /* ptr to regs */
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callr r3
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/* Restore regsisters and return from exception*/
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_exception_return:
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ldw r1, 4(sp)
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ldw r2, 8(sp)
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ldw r3, 12(sp)
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ldw r4, 16(sp)
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ldw r5, 20(sp)
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ldw r6, 24(sp)
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ldw r7, 28(sp)
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ldw r8, 32(sp)
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ldw r9, 36(sp)
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ldw r10, 40(sp)
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ldw r11, 44(sp)
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ldw r12, 48(sp)
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ldw r13, 52(sp)
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ldw r14, 56(sp)
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ldw r15, 60(sp)
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ldw r16, 64(sp)
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ldw r17, 68(sp)
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ldw r19, 72(sp)
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ldw r19, 76(sp)
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ldw r20, 80(sp)
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ldw r21, 84(sp)
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ldw r22, 88(sp)
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ldw r23, 92(sp)
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ldw r24, 96(sp)
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ldw r25, 100(sp)
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ldw r26, 104(sp)
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ldw r27, 108(sp)
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ldw r28, 112(sp)
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ldw r29, 116(sp)
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ldw r30, 120(sp)
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ldw r31, 124(sp)
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addi sp, sp, (33*4)
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eret
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/*-------------------------------------------------------------*/
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