459 lines
14 KiB
C
459 lines
14 KiB
C
/*
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* (C) Copyright 2005
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* John Otken, jotken@softadvances.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <ppc4xx.h>
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#include <asm/processor.h>
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#include <spd_sdram.h>
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#include "epld.h"
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extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
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/*************************************************************************
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* int board_early_init_f()
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*
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************************************************************************/
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int board_early_init_f(void)
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{
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volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
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mtebc( pb0ap, 0x03800000 ); /* set chip selects */
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mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
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mtebc( pb1ap, 0x03800000 );
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mtebc( pb1cr, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */
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mtebc( pb2ap, 0x03800000 );
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mtebc( pb2cr, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */
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mtdcr( uic1sr, 0xffffffff ); /* Clear all interrupts */
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mtdcr( uic1er, 0x00000000 ); /* disable all interrupts */
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mtdcr( uic1cr, 0x00000000 ); /* Set Critical / Non Critical interrupts */
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mtdcr( uic1pr, 0x7fff83ff ); /* Set Interrupt Polarities */
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mtdcr( uic1tr, 0x001f8000 ); /* Set Interrupt Trigger Levels */
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mtdcr( uic1vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
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mtdcr( uic1sr, 0x00000000 ); /* clear all interrupts */
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mtdcr( uic1sr, 0xffffffff );
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mtdcr( uic0sr, 0xffffffff ); /* Clear all interrupts */
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mtdcr( uic0er, 0x00000000 ); /* disable all interrupts excepted cascade */
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mtdcr( uic0cr, 0x00000001 ); /* Set Critical / Non Critical interrupts */
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mtdcr( uic0pr, 0xffffffff ); /* Set Interrupt Polarities */
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mtdcr( uic0tr, 0x01000004 ); /* Set Interrupt Trigger Levels */
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mtdcr( uic0vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
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mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */
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mtdcr( uic0sr, 0xffffffff );
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x->ethuart &= ~EPLD2_RESET_ETH_N; /* put Ethernet+PHY in reset */
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return 0;
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}
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/*************************************************************************
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* int misc_init_r()
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*
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************************************************************************/
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int misc_init_r(void)
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{
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volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
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x->ethuart |= EPLD2_RESET_ETH_N; /* take Ethernet+PHY out of reset */
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return 0;
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}
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/*************************************************************************
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* int checkboard()
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*
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************************************************************************/
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int checkboard(void)
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{
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char *s = getenv("serial#");
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printf("Board: Luan - AMCC PPC440SP Evaluation Board");
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if (s != NULL) {
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puts(", serial# ");
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puts(s);
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}
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putc('\n');
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return 0;
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}
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/*************************************************************************
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* long int fixed_sdram()
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*
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************************************************************************/
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static long int fixed_sdram(void)
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{ /* DDR2 init from BDI2000 script */
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mtdcr( 0x10, 0x00000021 ); /* MCIF0_MCOPT2 - zero DCEN bit */
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mtdcr( 0x11, 0x84000000 );
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mtdcr( 0x10, 0x00000020 ); /* MCIF0_MCOPT1 - no ECC, 64 bits, 4 banks, DDR2 */
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mtdcr( 0x11, 0x2D122000 );
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mtdcr( 0x10, 0x00000026 ); /* MCIF0_CODT - die termination on */
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mtdcr( 0x11, 0x00800026 );
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mtdcr( 0x10, 0x00000081 ); /* MCIF0_WRDTR - Write DQS Adv 90 + Fractional DQS Delay */
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mtdcr( 0x11, 0x82000800 );
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mtdcr( 0x10, 0x00000080 ); /* MCIF0_CLKTR - advance addr clock by 180 deg */
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mtdcr( 0x11, 0x80000000 );
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mtdcr( 0x10, 0x00000040 ); /* MCIF0_MB0CF - turn on CS0, N x 10 coll */
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mtdcr( 0x11, 0x00000201 );
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mtdcr( 0x10, 0x00000044 ); /* MCIF0_MB1CF - turn on CS0, N x 10 coll */
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mtdcr( 0x11, 0x00000201 );
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mtdcr( 0x10, 0x00000030 ); /* MCIF0_RTR - refresh every 7.8125uS */
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mtdcr( 0x11, 0x08200000 );
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mtdcr( 0x10, 0x00000085 ); /* MCIF0_SDTR1 - timing register 1 */
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mtdcr( 0x11, 0x80201000 );
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mtdcr( 0x10, 0x00000086 ); /* MCIF0_SDTR2 - timing register 2 */
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mtdcr( 0x11, 0x42103242 );
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mtdcr( 0x10, 0x00000087 ); /* MCIF0_SDTR3 - timing register 3 */
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mtdcr( 0x11, 0x0C100D14 );
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mtdcr( 0x10, 0x00000088 ); /* MCIF0_MMODE - CAS is 4 cycles */
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mtdcr( 0x11, 0x00000642 );
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mtdcr( 0x10, 0x00000089 ); /* MCIF0_MEMODE - diff DQS disabled */
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mtdcr( 0x11, 0x00000400 ); /* ODT term disabled */
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mtdcr( 0x10, 0x00000050 ); /* MCIF0_INITPLR0 - NOP */
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mtdcr( 0x11, 0x81b80000 );
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mtdcr( 0x10, 0x00000051 ); /* MCIF0_INITPLR1 - PRE */
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mtdcr( 0x11, 0x82100400 );
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mtdcr( 0x10, 0x00000052 ); /* MCIF0_INITPLR2 - EMR2 */
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mtdcr( 0x11, 0x80820000 );
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mtdcr( 0x10, 0x00000053 ); /* MCIF0_INITPLR3 - EMR3 */
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mtdcr( 0x11, 0x80830000 );
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mtdcr( 0x10, 0x00000054 ); /* MCIF0_INITPLR4 - EMR DLL ENABLE */
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mtdcr( 0x11, 0x80810000 );
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mtdcr( 0x10, 0x00000055 ); /* MCIF0_INITPLR5 - MR DLL RESET */
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mtdcr( 0x11, 0x80800542 );
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mtdcr( 0x10, 0x00000056 ); /* MCIF0_INITPLR6 - PRE */
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mtdcr( 0x11, 0x82100400 );
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mtdcr( 0x10, 0x00000057 ); /* MCIF0_INITPLR7 - refresh */
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mtdcr( 0x11, 0x99080000 );
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mtdcr( 0x10, 0x00000058 ); /* MCIF0_INITPLR8 */
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mtdcr( 0x11, 0x99080000 );
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mtdcr( 0x10, 0x00000059 ); /* MCIF0_INITPLR9 */
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mtdcr( 0x11, 0x99080000 );
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mtdcr( 0x10, 0x0000005A ); /* MCIF0_INITPLR10 */
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mtdcr( 0x11, 0x99080000 );
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mtdcr( 0x10, 0x0000005B ); /* MCIF0_INITPLR11 - MR */
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mtdcr( 0x11, 0x80800442 );
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mtdcr( 0x10, 0x0000005C ); /* MCIF0_INITPLR12 - EMR OCD Default */
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mtdcr( 0x11, 0x80810380 );
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mtdcr( 0x10, 0x0000005D ); /* MCIF0_INITPLR13 - EMR OCD exit */
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mtdcr( 0x11, 0x80810000 );
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udelay( 10*1000 );
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mtdcr( 0x10, 0x00000021 ); /* MCIF0_MCOPT2 - execute preloaded init */
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mtdcr( 0x11, 0x28000000 ); /* set DC_EN */
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udelay( 100*1000 );
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mtdcr( 0x40, 0x0000F800 ); /* MQ0_B0BAS: base addr 00000000 / 256MB */
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mtdcr( 0x41, 0x1000F800 ); /* MQ0_B1BAS: base addr 10000000 / 256MB */
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mtdcr( 0x10, 0x00000078 ); /* MCIF0_RDCC - auto set read stage */
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mtdcr( 0x11, 0x00000000 );
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mtdcr( 0x10, 0x00000070 ); /* MCIF0_RQDC - read DQS delay control */
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mtdcr( 0x11, 0x8000003A ); /* enabled, frac DQS delay */
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mtdcr( 0x10, 0x00000074 ); /* MCIF0_RFDC - two clock feedback delay */
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mtdcr( 0x11, 0x00000200 );
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return 512 << 20;
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}
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/*************************************************************************
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* long int initdram
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*
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************************************************************************/
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long int initdram( int board_type )
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{
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long dram_size = 0;
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#if defined(CONFIG_SPD_EEPROM)
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dram_size = spd_sdram (0);
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#else
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dram_size = fixed_sdram ();
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#endif
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return dram_size;
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}
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/*************************************************************************
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* int testdram()
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*
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************************************************************************/
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#if defined(CFG_DRAM_TEST)
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int testdram(void)
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{
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unsigned long *mem = (unsigned long *) 0;
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const unsigned long kend = (1024 / sizeof(unsigned long));
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unsigned long k, n;
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mtmsr(0);
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for (k = 0; k < CFG_KBYTES_SDRAM;
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++k, mem += (1024 / sizeof(unsigned long))) {
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if ((k & 1023) == 0) {
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printf("%3d MB\r", k / 1024);
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}
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memset(mem, 0xaaaaaaaa, 1024);
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for (n = 0; n < kend; ++n) {
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if (mem[n] != 0xaaaaaaaa) {
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printf("SDRAM test fails at: %08x\n",
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(uint) & mem[n]);
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return 1;
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}
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}
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memset(mem, 0x55555555, 1024);
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for (n = 0; n < kend; ++n) {
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if (mem[n] != 0x55555555) {
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printf("SDRAM test fails at: %08x\n",
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(uint) & mem[n]);
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return 1;
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}
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}
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}
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printf("SDRAM test passes\n");
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return 0;
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}
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#endif
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/*************************************************************************
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* pci_pre_init
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*
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* This routine is called just prior to registering the hose and gives
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* the board the opportunity to check things. Returning a value of zero
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* indicates that things are bad & PCI initialization should be aborted.
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*
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* Different boards may wish to customize the pci controller structure
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* (add regions, override default access routines, etc) or perform
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* certain pre-initialization actions.
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*
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************************************************************************/
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#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
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int pci_pre_init( struct pci_controller *hose )
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{
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unsigned long strap;
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/*--------------------------------------------------------------------------+
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* The luan board is always configured as the host & requires the
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* PCI arbiter to be enabled.
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*--------------------------------------------------------------------------*/
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mfsdr(sdr_sdstp1, strap);
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if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
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printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
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return 0;
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}
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return 1;
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}
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#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
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/*************************************************************************
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* pci_target_init
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*
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* The bootstrap configuration provides default settings for the pci
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* inbound map (PIM). But the bootstrap config choices are limited and
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* may not be sufficient for a given board.
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*
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************************************************************************/
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#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
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void pci_target_init(struct pci_controller *hose)
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{
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DECLARE_GLOBAL_DATA_PTR;
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/*--------------------------------------------------------------------------+
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* Disable everything
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*--------------------------------------------------------------------------*/
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out32r( PCIX0_PIM0SA, 0 ); /* disable */
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out32r( PCIX0_PIM1SA, 0 ); /* disable */
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out32r( PCIX0_PIM2SA, 0 ); /* disable */
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out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
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/*--------------------------------------------------------------------------+
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* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
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* options to not support sizes such as 128/256 MB.
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*--------------------------------------------------------------------------*/
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out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
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out32r( PCIX0_PIM0LAH, 0 );
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out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
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out32r( PCIX0_BAR0, 0 );
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/*--------------------------------------------------------------------------+
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* Program the board's subsystem id/vendor id
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*--------------------------------------------------------------------------*/
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out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
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out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
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out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
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}
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#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
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/*************************************************************************
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* is_pci_host
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*
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* This routine is called to determine if a pci scan should be
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* performed. With various hardware environments (especially cPCI and
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* PPMC) it's insufficient to depend on the state of the arbiter enable
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* bit in the strap register, or generic host/adapter assumptions.
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*
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* Rather than hard-code a bad assumption in the general 440 code, the
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* 440 pci code requires the board to decide at runtime.
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*
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* Return 0 for adapter mode, non-zero for host (monarch) mode.
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*
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*
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************************************************************************/
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#if defined(CONFIG_PCI)
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int is_pci_host(struct pci_controller *hose)
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{
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return 1;
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}
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#endif /* defined(CONFIG_PCI) */
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/*************************************************************************
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* hw_watchdog_reset
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*
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* This routine is called to reset (keep alive) the watchdog timer
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*
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************************************************************************/
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#if defined(CONFIG_HW_WATCHDOG)
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void hw_watchdog_reset(void)
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{
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}
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#endif
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/*************************************************************************
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* int on_off()
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*
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************************************************************************/
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static int on_off( const char *s )
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{
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if (strcmp(s, "on") == 0) {
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return 1;
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} else if (strcmp(s, "off") == 0) {
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return 0;
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}
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return -1;
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}
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/*************************************************************************
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* void l2cache_disable()
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*
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************************************************************************/
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static void l2cache_disable(void)
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{
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mtdcr( l2_cache_cfg, 0 );
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}
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/*************************************************************************
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* void l2cache_enable()
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*
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************************************************************************/
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static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */
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{
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mtdcr( l2_cache_cfg, 0x80000000 ); /* enable L2_MODE L2_CFG[L2M] */
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mtdcr( l2_cache_addr, 0 ); /* set L2_ADDR with all zeros */
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mtdcr( l2_cache_cmd, 0x80000000 ); /* issue HCLEAR command via L2_CMD */
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while (!(mfdcr( l2_cache_stat ) & 0x80000000 )) ;; /* poll L2_SR for completion */
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mtdcr( l2_cache_cmd, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */
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mtdcr( l2_cache_cmd, 0x08000000 ); /* clear tag errors L2_CMD[CTE] */
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mtdcr( l2_cache_snp0, 0 ); /* snoop registers */
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mtdcr( l2_cache_snp1, 0 );
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__asm__ volatile ("sync"); /* msync */
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mtdcr( l2_cache_cfg, 0xe0000000 ); /* inst and data use L2 */
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__asm__ volatile ("sync");
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}
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/*************************************************************************
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* int l2cache_status()
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*
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************************************************************************/
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static int l2cache_status(void)
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{
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return (mfdcr( l2_cache_cfg ) & 0x60000000) != 0;
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}
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/*************************************************************************
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* int do_l2cache()
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*
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************************************************************************/
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int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] )
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{
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switch (argc) {
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case 2: /* on / off */
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switch (on_off(argv[1])) {
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case 0: l2cache_disable();
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break;
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case 1: l2cache_enable();
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break;
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}
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/* FALL TROUGH */
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case 1: /* get status */
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printf ("L2 Cache is %s\n",
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l2cache_status() ? "ON" : "OFF");
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return 0;
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default:
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printf ("Usage:\n%s\n", cmdtp->usage);
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return 1;
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}
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return 0;
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}
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U_BOOT_CMD(
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l2cache, 2, 1, do_l2cache,
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"l2cache - enable or disable L2 cache\n",
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"[on, off]\n"
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" - enable or disable L2 cache\n"
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);
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