1022 lines
15 KiB
C
1022 lines
15 KiB
C
/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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*******************************************************************************/
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/* Code for setting up pagetables or the protection unit,
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* and enabling the cache. */
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#include <config.h>
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#include <common.h>
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#include <asm/types.h>
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#include <command.h>
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#include "mvSysHwConfig.h"
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#if defined(MV_INCLUDE_MONT_EXT) && defined (MV_INCLUDE_MONT_MPU)
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#include "mvTypes.h"
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#include "mvCtrlEnvLib.h"
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#include "mvCpuIf.h"
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#include "cpu/mvCpu.h"
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#ifndef MV_TINY_IMAGE
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/* This file refers to the A.R.M.--The ARM Architecture Reference Manual */
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typedef enum _access_type{
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/* priveliged - user */
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NO_NO = 0 , /* No access _ No Access */
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RW_NO = 1, /* Read/Write _ No Access */
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RW_RO = 2 , /* Read/Write _ Read Only */
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RW_RW = 3, /* Read/Write _ Read/Write */
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RO_NO = 5 , /* Read Only _ No Access */
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RO_RO = 6 /* Read Only _ Read Only */
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}ACCESS_TYPE;
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typedef enum _region_size{
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REG_4KB = 0xB,
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REG_8KB = 0xC,
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REG_16KB = 0xD,
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REG_32KB = 0xE,
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REG_64KB = 0xF,
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REG_128KB = 0x10,
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REG_256KB = 0x11,
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REG_512KB = 0x12,
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REG_1MB = 0x13,
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REG_2MB = 0x14,
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REG_4MB = 0x15,
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REG_8MB = 0x16,
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REG_16MB = 0x17,
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REG_32MB = 0x18,
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REG_64MB = 0x19,
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REG_128MB = 0x1A,
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REG_256MB = 0x1B,
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REG_512MB = 0x1C,
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REG_1GB = 0x1D,
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REG_2GB = 0x1E,
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REG_4GB = 0x1F
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}REGION_SIZE;
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typedef unsigned char bool;
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typedef struct _mpu_region
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{
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unsigned int base;
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REGION_SIZE size;
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bool iCache;
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bool dCache;
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bool wb;
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ACCESS_TYPE dAccess;
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ACCESS_TYPE iAccess;
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}MPU_REGION;
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typedef enum _cache_type{
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D_CACHE,
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I_CACHE
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}CACHE_TYPE;
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typedef enum _mem_type{
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D_MEM,
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I_MEM
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}MEM_TYPE;
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static unsigned int sizeToBits(unsigned int size)
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{
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switch (size)
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{
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case 0x00001000:
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return REG_4KB;
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break;
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case 0x00002000:
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return REG_8KB;
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break;
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case 0x00004000:
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return REG_16KB;
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break;
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case 0x00008000:
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return REG_32KB;
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break;
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case 0x00010000:
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return REG_64KB;
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break;
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case 0x00020000:
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return REG_128KB;
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break;
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case 0x00040000:
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return REG_256KB;
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break;
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case 0x00080000:
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return REG_512KB;
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break;
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case 0x00100000:
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return REG_1MB;
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break;
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case 0x00200000:
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return REG_2MB;
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break;
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case 0x00400000:
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return REG_4MB;
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break;
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case 0x00800000:
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return REG_8MB;
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break;
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case 0x01000000:
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return REG_16MB;
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break;
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case 0x02000000:
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return REG_32MB;
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break;
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case 0x04000000:
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return REG_64MB;
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break;
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case 0x08000000:
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return REG_128MB;
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break;
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case 0x10000000:
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return REG_256MB;
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break;
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case 0x20000000:
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return REG_512MB;
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break;
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case 0x40000000:
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return REG_1GB;
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break;
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case 0x80000000:
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return REG_2GB;
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break;
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}
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return 0;
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}
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static void printSizeOfRegion(REGION_SIZE bits)
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{
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switch (bits)
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{
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case REG_4KB:
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printf("4KB");
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break;
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case REG_8KB:
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printf("8KB");
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break;
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case REG_16KB:
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printf("16KB");
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break;
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case REG_32KB:
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printf("32KB");
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break;
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case REG_64KB:
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printf("64KB");
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break;
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case REG_128KB:
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printf("128KB");
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break;
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case REG_256KB:
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printf("256KB");
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break;
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case REG_512KB:
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printf("512KB");
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break;
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case REG_1MB:
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printf("1MB");
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break;
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case REG_2MB:
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printf("2MB");
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break;
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case REG_4MB:
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printf("4MB");
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break;
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case REG_8MB:
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printf("8MB");
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break;
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case REG_16MB:
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printf("16MB");
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break;
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case REG_32MB:
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printf("32MB");
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break;
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case REG_64MB:
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printf("64MB");
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break;
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case REG_128MB:
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printf("128MB");
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break;
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case REG_256MB:
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printf("256MB");
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break;
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case REG_512MB:
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printf("512MB");
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break;
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case REG_1GB:
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printf("1GB");
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case REG_2GB:
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printf("2GB");
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break;
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case REG_4GB:
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printf("4GB");
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break;
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}
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}
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/*
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get Control register
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*/
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unsigned int get_control(void)
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{
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unsigned int value;
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__asm__ __volatile__(
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"mrc p15, 0, %0, c1, c0, 0\n"
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: "=r" (value)
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:
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: "memory");
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return value;
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}
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/*
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set Control register
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*/
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void set_control(unsigned int value)
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{
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__asm__ __volatile__(
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"mcr p15, 0, %0, c1, c0, 0\n"
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:
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: "r" (value));
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}
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/*
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get Write Buffer Configuration
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*/
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static unsigned int get_wb(void)
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{
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unsigned int value;
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__asm__ __volatile__(
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"mrc p15, 0, %0, c3, c0, 0\n"
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: "=r" (value)
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:
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: "memory");
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return value;
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}
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/*
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set Write Buffer Configuration
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*/
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static void set_wb(unsigned int value)
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{
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__asm__ __volatile__(
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"mcr p15, 0, %0, c3, c0, 0\n"
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:
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: "r" (value));
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}
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/*
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Read cache configuration
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*/
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static unsigned int get_cache_config(CACHE_TYPE type)
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{
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unsigned int value = 0;
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switch (type)
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{
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case D_CACHE:
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__asm__ __volatile__(
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"mrc p15, 0, %0, c2, c0, 0\n"
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: "=r" (value)
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:
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: "memory");
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break;
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case I_CACHE:
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__asm__ __volatile__(
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"mrc p15, 0, %0, c2, c0, 1\n"
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: "=r" (value)
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:
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: "memory");
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break;
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}
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return value;
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}
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/*
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Write cache configuration
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*/
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static void set_cache_config(CACHE_TYPE type,unsigned int value)
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{
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switch (type)
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{
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case D_CACHE:
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__asm__ __volatile__(
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"mcr p15, 0, %0, c2, c0, 0\n"
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:
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: "r" (value));
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break;
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case I_CACHE:
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__asm__ __volatile__(
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"mcr p15, 0, %0, c2, c0, 1\n"
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:
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: "r" (value));
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break;
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}
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}
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/*
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Read access permision
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*/
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static unsigned int get_access(MEM_TYPE type)
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{
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unsigned int value = 0;
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switch (type)
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{
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case D_MEM:
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__asm__ __volatile__(
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"mrc p15, 0, %0, c5, c0, 2\n"
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: "=r" (value)
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:
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: "memory");
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break;
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case I_MEM:
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__asm__ __volatile__(
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"mrc p15, 0, %0, c5, c0, 3\n"
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: "=r" (value)
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:
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: "memory");
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break;
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}
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return value;
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}
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/*
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Write cache configuration
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*/
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static void set_access(MEM_TYPE type,unsigned int value)
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{
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switch (type)
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{
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case D_MEM:
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__asm__ __volatile__(
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"mcr p15, 0, %0, c5, c0, 2\n"
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:
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: "r" (value));
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break;
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case I_MEM:
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__asm__ __volatile__(
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"mcr p15, 0, %0, c5, c0, 3\n"
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:
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: "r" (value));
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break;
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}
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}
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/*
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get protection region size\base\enable
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*/
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unsigned int get_prot_attrib(int region)
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{
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unsigned int value = 0;
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switch (region)
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{
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case 0:
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__asm__ __volatile__(
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"mrc p15, 0, %0, c6, c0, 0\n"
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: "=r" (value)
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:
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: "memory");
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break;
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case 1:
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__asm__ __volatile__(
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"mrc p15, 0, %0, c6, c1, 0\n"
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: "=r" (value)
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:
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: "memory");
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break;
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case 2:
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__asm__ __volatile__(
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"mrc p15, 0, %0, c6, c2, 0\n"
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: "=r" (value)
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:
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: "memory");
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break;
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case 3:
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__asm__ __volatile__(
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"mrc p15, 0, %0, c6, c3, 0\n"
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: "=r" (value)
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:
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: "memory");
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break;
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case 4:
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__asm__ __volatile__(
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"mrc p15, 0, %0, c6, c4, 0\n"
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: "=r" (value)
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:
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: "memory");
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break;
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case 5:
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__asm__ __volatile__(
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"mrc p15, 0, %0, c6, c5, 0\n"
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: "=r" (value)
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:
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: "memory");
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break;
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case 6:
|
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__asm__ __volatile__(
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"mrc p15, 0, %0, c6, c6, 0\n"
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: "=r" (value)
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:
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: "memory");
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break;
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case 7:
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__asm__ __volatile__(
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"mrc p15, 0, %0, c6, c7, 0\n"
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: "=r" (value)
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:
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: "memory");
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break;
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|
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}
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return value;
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}
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|
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/*
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set protection region size\base\enable
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*/
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static void set_prot_attrib(int region,unsigned int value)
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{
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switch (region)
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{
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case 0:
|
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__asm__ __volatile__(
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"mcr p15, 0, %0, c6, c0, 0\n"
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:
|
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: "r" (value));
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|
|
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break;
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case 1:
|
|
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|
__asm__ __volatile__(
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|
"mcr p15, 0, %0, c6, c1, 0\n"
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:
|
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: "r" (value));
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break;
|
|
case 2:
|
|
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|
__asm__ __volatile__(
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|
"mcr p15, 0, %0, c6, c2, 0\n"
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:
|
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: "r" (value));
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break;
|
|
case 3:
|
|
|
|
__asm__ __volatile__(
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|
"mcr p15, 0, %0, c6, c3, 0\n"
|
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:
|
|
: "r" (value));
|
|
|
|
break;
|
|
case 4:
|
|
|
|
__asm__ __volatile__(
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|
"mcr p15, 0, %0, c6, c4, 0\n"
|
|
:
|
|
: "r" (value));
|
|
|
|
break;
|
|
case 5:
|
|
|
|
__asm__ __volatile__(
|
|
"mcr p15, 0, %0, c6, c5, 0\n"
|
|
:
|
|
: "r" (value));
|
|
|
|
break;
|
|
case 6:
|
|
|
|
__asm__ __volatile__(
|
|
"mcr p15, 0, %0, c6, c6, 0\n"
|
|
:
|
|
: "r" (value));
|
|
|
|
break;
|
|
case 7:
|
|
|
|
__asm__ __volatile__(
|
|
"mcr p15, 0, %0, c6, c7, 0\n"
|
|
:
|
|
: "r" (value));
|
|
|
|
break;
|
|
|
|
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
static void createMPUEntry(int region,MPU_REGION *mpuEntry)
|
|
{
|
|
unsigned int value = 0;
|
|
|
|
/* set data cache attributes */
|
|
value = get_cache_config(D_CACHE);
|
|
|
|
if (mpuEntry->dCache)
|
|
{
|
|
value |= (1<< region);
|
|
}
|
|
else
|
|
{
|
|
value &= ~(1<< region);
|
|
}
|
|
|
|
set_cache_config(D_CACHE,value);
|
|
|
|
/* set instruction cache attributes */
|
|
value = get_cache_config(I_CACHE);
|
|
|
|
if (mpuEntry->iCache)
|
|
{
|
|
value |= (1<< region);
|
|
}
|
|
else
|
|
{
|
|
value &= ~(1<< region);
|
|
}
|
|
|
|
set_cache_config(I_CACHE,value);
|
|
|
|
/* set write buffer */
|
|
|
|
value = get_wb();
|
|
|
|
if (mpuEntry->wb)
|
|
{
|
|
value |= (1<< region);
|
|
}
|
|
else
|
|
{
|
|
value &= ~(1<< region);
|
|
}
|
|
|
|
set_wb(value);
|
|
|
|
/* set access permision for data accesses*/
|
|
|
|
value = get_access(D_MEM);
|
|
value &= ~(0xf << (region*4));
|
|
value |= (mpuEntry->dAccess << (region*4));
|
|
set_access(D_MEM , value);
|
|
|
|
/* set access permision for instruction accesses*/
|
|
|
|
value = get_access(I_MEM);
|
|
value &= ~(0xf << (region*4));
|
|
value |= (mpuEntry->iAccess << (region*4));
|
|
set_access(I_MEM, value);
|
|
|
|
|
|
|
|
/*set base and size and enable*/
|
|
value = 0;
|
|
value |= (mpuEntry->base) & (0xFFFFF << 12);
|
|
value |= ( mpuEntry->size << 1);
|
|
value |= 1;
|
|
|
|
set_prot_attrib(region,value);
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
/* These are all the bits currently defined for the control register */
|
|
/* A.R.M. 7.4.2 */
|
|
#define MPU_V 0x2000 /* alternae vector select */
|
|
#define MPU_I 0x1000 /* Instruction cache */
|
|
#define MPU_B 0x0080 /* big endian */
|
|
#define MPU_RES 0x00F79 /* reserved bits should be 1 */
|
|
#define MPU_C 0x0004 /* data cache */
|
|
#define MPU_P 0x0001 /* protection unit */
|
|
|
|
|
|
|
|
/*
|
|
* The functions below take arguments to specify which "caches" the
|
|
* action is to be directed at. For the I-cache, pass "MMU_I". For
|
|
* the D-cache, "MMU_C". For both, pass "MMU_ID". For combined ID-Cache
|
|
* processors, use "MMU_C"
|
|
*/
|
|
#define MPU_ID (MPU_I + MPU_C)
|
|
|
|
|
|
int mpuMap(void)
|
|
{
|
|
|
|
unsigned int value;
|
|
int region;
|
|
|
|
value = get_control();
|
|
|
|
if (value & MPU_P)
|
|
{
|
|
printf("\nProtection Unit:\n");
|
|
|
|
for (region = 1 ; region < 8 ; region++)
|
|
{
|
|
value = get_prot_attrib(region);
|
|
/* check if region is enabled */
|
|
if (value & 1)
|
|
{
|
|
printf("region %d base=0x%08x size =",region,value & (0xFFFFF << 12));
|
|
printSizeOfRegion(((value & (0x1f << 1)) >> 1));
|
|
|
|
value = get_cache_config(D_CACHE);
|
|
|
|
if (value & (1 << region))
|
|
{
|
|
printf(" :DCache enabled - ");
|
|
}
|
|
else
|
|
{
|
|
printf(" :DCache disabled - ");
|
|
}
|
|
|
|
value = get_cache_config(I_CACHE);
|
|
|
|
if (value & (1 << region))
|
|
{
|
|
printf("ICache enabled - ");
|
|
}
|
|
else
|
|
{
|
|
printf("ICache disabled - ");
|
|
}
|
|
|
|
value = get_wb();
|
|
|
|
if (value & (1 << region))
|
|
{
|
|
printf("Bufferable");
|
|
}
|
|
else
|
|
{
|
|
printf("non Bufferable");
|
|
}
|
|
|
|
printf("\n");
|
|
|
|
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
else
|
|
{
|
|
printf("MPU is disabled\n");
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
|
|
|
|
|
|
/* Flush the cache(s).
|
|
*/
|
|
inline void mpuInvCache(unsigned caches)
|
|
{
|
|
unsigned long dummy = 0;
|
|
|
|
switch (caches)
|
|
{
|
|
case MPU_C:
|
|
__asm__ __volatile__(
|
|
"mcr p15, 0, %0, c7, c6, 0\n"
|
|
:
|
|
: "r" (dummy));
|
|
break;
|
|
case MPU_I:
|
|
__asm__ __volatile__(
|
|
"mcr p15, 0, %0, c7, c5, 0\n"
|
|
:
|
|
: "r" (dummy));
|
|
break;
|
|
case MPU_ID:
|
|
__asm__ __volatile__(
|
|
"mcr p15, 0, %0, c7, c7, 0\n"
|
|
:
|
|
: "r" (dummy));
|
|
break;
|
|
}
|
|
}
|
|
|
|
|
|
/* Enable the cache/MMU/TLB etc.
|
|
*/
|
|
inline void _cpuCfgEnable(unsigned long flags, MV_BOOL enable)
|
|
{
|
|
unsigned long tmp;
|
|
|
|
if (enable == MV_TRUE)
|
|
{
|
|
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (tmp));
|
|
tmp |= flags;
|
|
asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (tmp));
|
|
}
|
|
else
|
|
{
|
|
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (tmp));
|
|
tmp &= ~flags;
|
|
asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (tmp));
|
|
}
|
|
}
|
|
|
|
/* Disable the I/D cache.
|
|
*/
|
|
|
|
inline void _disableIDCache(void)
|
|
{
|
|
unsigned long tmp;
|
|
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (tmp));
|
|
tmp &= ~MPU_ID;
|
|
asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (tmp));
|
|
|
|
/* invalidate I/D-cache */
|
|
tmp = 0;
|
|
asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (tmp));
|
|
|
|
}
|
|
|
|
|
|
void MPU_Init(void)
|
|
{
|
|
MPU_REGION mpuEntry;
|
|
#if defined(MV_INCLUDE_SDRAM_CS1)
|
|
MV_CPU_DEC_WIN win;
|
|
MV_TARGET target;
|
|
unsigned int totalSize=0;
|
|
#endif
|
|
int region=0;
|
|
char *env;
|
|
|
|
printf("Intializing Protection Unit\n");
|
|
_disableIDCache();
|
|
|
|
/* enable I cache - doesn't need MPU enabling */
|
|
/*_enable(MPU_RES);*/
|
|
|
|
/* set region 0 - include all memory and have I and D caches disabled
|
|
and write buffer disabled */
|
|
|
|
mpuEntry.base = 0;
|
|
mpuEntry.size = REG_4GB;
|
|
mpuEntry.dCache = 0;
|
|
mpuEntry.iCache = 0;
|
|
mpuEntry.wb = 0;
|
|
mpuEntry.iAccess = NO_NO;
|
|
mpuEntry.dAccess = NO_NO;
|
|
|
|
createMPUEntry(region++ , &mpuEntry);
|
|
|
|
|
|
|
|
/* set region 1 - CS0 DRAM region */
|
|
|
|
mpuEntry.base = mvCpuIfTargetWinBaseLowGet(SDRAM_CS0);
|
|
|
|
mpuEntry.size = sizeToBits(mvCpuIfTargetWinSizeGet(SDRAM_CS0));
|
|
|
|
mpuEntry.dCache = 0;
|
|
mpuEntry.iCache = 1;
|
|
mpuEntry.wb = 0;
|
|
|
|
mpuEntry.iAccess = RW_RW;
|
|
mpuEntry.dAccess = RW_RW;
|
|
|
|
createMPUEntry(region++ , &mpuEntry);
|
|
|
|
|
|
/* set region 2 - CS0-CS3 DRAM region */
|
|
#if defined(MV_INCLUDE_SDRAM_CS1)
|
|
for (target = SDRAM_CS1 ; target < MV_DRAM_MAX_CS ; target++)
|
|
{
|
|
mvCpuIfTargetWinGet(target, &win);
|
|
|
|
if (win.enable) break;
|
|
}
|
|
|
|
target = SDRAM_CS1;
|
|
mpuEntry.base = mvCpuIfTargetWinBaseLowGet(target);
|
|
|
|
for (target = SDRAM_CS1; target < MV_DRAM_MAX_CS ; target++)
|
|
{
|
|
totalSize += mvCpuIfTargetWinSizeGet(target);
|
|
}
|
|
|
|
|
|
mpuEntry.size = sizeToBits(totalSize);
|
|
|
|
mpuEntry.dCache = 0;
|
|
mpuEntry.iCache = 0;
|
|
mpuEntry.wb = 0;
|
|
|
|
mpuEntry.iAccess = RW_RW;
|
|
mpuEntry.dAccess = RW_RW;
|
|
#endif
|
|
|
|
env = getenv("dramCached");
|
|
|
|
if((!env)||( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ))
|
|
{
|
|
setenv("dramCached","yes");
|
|
|
|
mpuEntry.dCache = 1;
|
|
mpuEntry.iCache = 1;
|
|
mpuEntry.wb = 1;
|
|
|
|
}
|
|
|
|
createMPUEntry(region++ , &mpuEntry);
|
|
|
|
/* set region 3 - devices region */
|
|
mpuEntry.base = 0xF0000000;
|
|
|
|
mpuEntry.size = REG_256MB;
|
|
|
|
mpuEntry.dCache = 0;
|
|
mpuEntry.iCache = 0;
|
|
mpuEntry.wb = 0;
|
|
|
|
mpuEntry.iAccess = RW_RW;
|
|
mpuEntry.dAccess = RW_RW;
|
|
|
|
createMPUEntry(region++ , &mpuEntry);
|
|
|
|
/* set region 4 - pci region */
|
|
mpuEntry.base = 0x90000000;
|
|
|
|
mpuEntry.size = REG_256MB;
|
|
|
|
mpuEntry.dCache = 0;
|
|
mpuEntry.iCache = 0;
|
|
mpuEntry.wb = 0;
|
|
|
|
mpuEntry.iAccess = RW_RW;
|
|
mpuEntry.dAccess = RW_RW;
|
|
|
|
env = getenv("pciCached");
|
|
|
|
if(!env)
|
|
setenv("pciCached","no");
|
|
else
|
|
{
|
|
if( ( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) )
|
|
{
|
|
mpuEntry.dCache = 1;
|
|
mpuEntry.iCache = 1;
|
|
mpuEntry.wb = 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
createMPUEntry(region++ , &mpuEntry);
|
|
|
|
/* set region 5 - stack pointer */
|
|
mpuEntry.base = 0xF00000;
|
|
|
|
mpuEntry.size = REG_64KB;
|
|
|
|
mpuEntry.dCache = 1;
|
|
mpuEntry.iCache = 1;
|
|
mpuEntry.wb = 1;
|
|
|
|
mpuEntry.iAccess = RW_RW;
|
|
mpuEntry.dAccess = RW_RW;
|
|
|
|
|
|
createMPUEntry(region++ , &mpuEntry);
|
|
|
|
|
|
/*mpuInvCache(MPU_ID);*/
|
|
/* write to control register :-
|
|
* I-cache on, 32-bit data and program space,
|
|
* write-buffer on, D-cache on, MMU on
|
|
*/
|
|
_cpuCfgEnable((MPU_I|MPU_C|MPU_P|MPU_RES), MV_TRUE);
|
|
|
|
return ;
|
|
}
|
|
#endif
|
|
|
|
#endif /* MV_INCLUDE_MONT_EXT */
|
|
|