180 lines
9.0 KiB
C
180 lines
9.0 KiB
C
/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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This software file (the "File") is owned and distributed by Marvell
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International Ltd. and/or its affiliates ("Marvell") under the following
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alternative licensing terms. Once you have made an election to distribute the
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File under one of the following license alternatives, please (i) delete this
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introductory statement regarding license alternatives, (ii) delete the two
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license alternatives that you have not elected to use and (iii) preserve the
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Marvell copyright notice above.
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********************************************************************************
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Marvell Commercial License Option
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If you received this File from Marvell and you have entered into a commercial
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license agreement (a "Commercial License") with Marvell, the File is licensed
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to you under the terms of the applicable Commercial License.
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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********************************************************************************
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Marvell BSD License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File under the following licensing terms.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Marvell nor the names of its contributors may be
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used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#ifndef __INCmvDramIfStaticInith
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#define __INCmvDramIfStaticInith
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#ifdef MV_STATIC_DRAM_ON_BOARD
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#define STATIC_DRAM_BANK_1
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#undef STATIC_DRAM_BANK_2
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#undef STATIC_DRAM_BANK_3
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#undef STATIC_DRAM_BANK_4
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#ifdef MV_DIMM_TS256MLQ72V5U
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#define STATIC_DRAM_BANK_2
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#define STATIC_DRAM_BANK_3
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#undef STATIC_DRAM_BANK_4
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#define STATIC_SDRAM_CONFIG_REG 0x4724481A /* offset 0x1400 - DMA reg-0xf1000814 */
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#define STATIC_SDRAM_DUNIT_CTRL_REG 0x37707450 /* offset 0x1404 - DMA reg-0xf100081c */
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#define STATIC_SDRAM_TIMING_CTRL_LOW_REG 0x11A13330 /* offset 0x1408 - DMA reg-0xf1000824 */
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#define STATIC_SDRAM_TIMING_CTRL_HIGH_REG 0x00000601 /* offset 0x140c - DMA reg-0xf1000828 */
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#define STATIC_SDRAM_ADDR_CTRL_REG 0x00001CB2 /* offset 0x1410 - DMA reg-0xf1000820 */
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#define STATIC_SDRAM_MODE_REG 0x00000642 /* offset 0x141c - DMA reg-0xf1000818 */
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#define STATIC_SDRAM_ODT_CTRL_LOW 0x030C030C /* 0x1494 */
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#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */
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#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000740F /* 0x149c */
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#define STATIC_SDRAM_EXT_MODE 0x00000404 /* 0x1420 */
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#define STATIC_SDRAM_DDR2_TIMING_LO 0x00074410 /* 0x1428 */
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#define STATIC_SDRAM_DDR2_TIMING_HI 0x00007441 /* 0x147C */
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#define STATIC_SDRAM_RANK0_SIZE_DIMM0 0x3FFF /* size bank0 dimm0 - DMA reg-0xf1000810 */
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#define STATIC_SDRAM_RANK1_SIZE_DIMM0 0x3FFF /* size bank1 dimm0 */
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#define STATIC_SDRAM_RANK0_SIZE_DIMM1 0x3FFF /* size bank0 dimm1 */
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#define STATIC_SDRAM_RANK1_SIZE_DIMM1 0x0 /* size bank1 dimm1 */
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#endif /* TS256MLQ72V5U */
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#ifdef MV_MT9VDDT3272AG
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/* one DIMM 256M */
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#define STATIC_SDRAM_CONFIG_REG 0x5820040d /* offset 0x1400 - DMA reg-0xf1000814 */
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#define STATIC_SDRAM_DUNIT_CTRL_REG 0xC4000540 /* offset 0x1404 - DMA reg-0xf100081c */
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#define STATIC_SDRAM_TIMING_CTRL_LOW_REG 0x01602220 /* offset 0x1408 - DMA reg-0xf1000824 */
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#define STATIC_SDRAM_TIMING_CTRL_HIGH_REG 0x0000000b /* offset 0x140c - DMA reg-0xf1000828 */
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#define STATIC_SDRAM_ADDR_CTRL_REG 0x00000012 /* offset 0x1410 - DMA reg-0xf1000820 */
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#define STATIC_SDRAM_MODE_REG 0x00000062 /* offset 0x141c - DMA reg-0xf1000818 */
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#define STATIC_SDRAM_RANK0_SIZE_DIMM0 0x0fff /* size bank0 dimm0 - DMA reg-0xf1000810 */
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#define STATIC_SDRAM_RANK0_SIZE_DIMM1 0x0 /* size bank0 dimm1 */
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#endif /* MV_MT9VDDT3272AG */
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#ifdef MV_D27RB12P
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/*
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Two DIMM 512M + ECC enabled, Registered DIMM CAS Latency 2.5
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*/
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#define STATIC_SDRAM_CONFIG_REG 0x6826081E /* offset 0x1400 - DMA reg-0xf1000814 */
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#define STATIC_SDRAM_DUNIT_CTRL_REG 0xC5000540 /* offset 0x1404 - DMA reg-0xf100081c */
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#define STATIC_SDRAM_TIMING_CTRL_LOW_REG 0x01501220 /* offset 0x1408 - DMA reg-0xf1000824 */
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#define STATIC_SDRAM_TIMING_CTRL_HIGH_REG 0x00000009 /* offset 0x140c - DMA reg-0xf1000828 */
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#define STATIC_SDRAM_ADDR_CTRL_REG 0x00000012 /* offset 0x1410 - DMA reg-0xf1000820 */
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#define STATIC_SDRAM_MODE_REG 0x00000062 /* offset 0x141c - DMA reg-0xf1000818 */
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#define STATIC_SDRAM_RANK0_SIZE_DIMM0 0x0FFF /* size bank0 dimm0 - DMA reg-0xf1000810 */
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#define STATIC_SDRAM_RANK0_SIZE_DIMM1 0x0FFF /* size bank0 dimm1 */
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#define STATIC_DRAM_BANK_2
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#define STATIC_DRAM_BANK_3
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#define STATIC_DRAM_BANK_4
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#endif /* mv_D27RB12P */
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#ifdef RD_MV645XX
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#define STATIC_MEM_TYPE MEM_TYPE_DDR2
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#define STATIC_DIMM_INFO_BANK0_SIZE 256
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/* DDR2 boards 256 MB*/
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#define STATIC_SDRAM_RANK0_SIZE_DIMM0 0x00000fff /* size bank0 dimm0 - DMA reg-0xf1000810 */
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#define STATIC_SDRAM_CONFIG_REG 0x07190618
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#define STATIC_SDRAM_MODE_REG 0x00000432
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#define STATIC_SDRAM_DUNIT_CTRL_REG 0xf4a03440
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#define STATIC_SDRAM_ADDR_CTRL_REG 0x00000022
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#define STATIC_SDRAM_TIMING_CTRL_LOW_REG 0x11712220
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#define STATIC_SDRAM_TIMING_CTRL_HIGH_REG 0x00000504
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#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000
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#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000
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#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000780f
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#define STATIC_SDRAM_EXT_MODE 0x00000440
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#define STATIC_SDRAM_DDR2_TIMING_LO 0x00063300
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#define STATIC_SDRAM_DDR2_TIMING_HI 0x00006330
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#endif /* RD_MV645XX */
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#if MV_DIMM_M3783354CZ3_CE6
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#define STATIC_SDRAM_RANK0_SIZE_DIMM0 0x00000FFF /* 0x2010 size bank0 dimm0 - DMA reg-0xf1000810 */
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#define STATIC_SDRAM_CONFIG_REG 0x07190618 /* 0x1400 */
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#define STATIC_SDRAM_MODE_REG 0x00000432 /* 0x141c */
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#define STATIC_SDRAM_DUNIT_CTRL_REG 0xf4a03440 /* 0x1404 */
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#define STATIC_SDRAM_ADDR_CTRL_REG 0x00000022 /* 0x1410 */
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#define STATIC_SDRAM_TIMING_CTRL_LOW_REG 0x11712220 /* 0x1408 */
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#define STATIC_SDRAM_TIMING_CTRL_HIGH_REG 0x00000504 /* 0x140c */
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#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */
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#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */
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#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000780f /* 0x149c */
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#define STATIC_SDRAM_EXT_MODE 0x00000440 /* 0x1420 */
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#define STATIC_SDRAM_DDR2_TIMING_LO 0x00063300 /* 0x1428 */
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#define STATIC_SDRAM_DDR2_TIMING_HI 0x00006330 /* 0x147C */
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#endif /* MV_DIMM_M3783354CZ3_CE6 */
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#endif /* MV_STATIC_DRAM_ON_BOARD */
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#endif /* __INCmvDramIfStaticInith */
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