323 lines
7.5 KiB
C
323 lines
7.5 KiB
C
/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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*******************************************************************************/
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#include <config.h>
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#include <common.h>
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#include "ddr2/mvDramIf.h"
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#include "mvOs.h"
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#include "mvBoardEnvLib.h"
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#include "ddr2/mvDramIfRegs.h"
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#include "mvCpuIfRegs.h"
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#ifdef DEBUG
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#define DB(x) x
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#else
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#define DB(x)
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#endif
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extern void i2c_init(int speed, int slaveaddr);
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extern void _start(void);
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extern unsigned int mvCpuPclkGet(void);
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extern void reset_cpu(void);
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extern int dramBoot;
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#ifdef MV_INC_DRAM_MFG_TEST
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static MV_VOID mvDramMfgTrst(void);
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static MV_STATUS mv_mem_test(MV_U32* pMem, MV_U32 pattern, MV_U32 count);
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static MV_STATUS mv_mem_cmp(MV_U32* pMem, MV_U32 pattern, MV_U32 count);
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#endif
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MV_VOID mvIntrfaceWidthPrint(MV_VOID)
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{
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printf(" 16bit width");
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}
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MV_VOID mvIntrfaceParamPrint(MV_VOID)
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{
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MV_U32 temp;
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printf("DRAM");
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switch((MV_REG_READ(0x141c) >> 4) & 0x7)
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{
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case 0x3: printf(" CAS Latency = 3");
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break;
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case 0x4: printf(" CAS Latency = 4");
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break;
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case 0x5: printf(" CAS Latency = 5");
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break;
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case 0x6: printf(" CAS Latency = 6");
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break;
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default: printf(" unknown CAL ");
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break;
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}
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temp = MV_REG_READ(0x1408);
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printf(" tRP = %d tRAS = %d tRCD=%d\n",
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((temp >> 8) & 0xf) + 1, ((temp >> 16) & 0x10) + (temp & 0xf) + 1, ((temp >> 4) & 0xf) + 1);
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}
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int dram_init (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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unsigned int i, dramTotalSize=0;
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char name[15];
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MV_32 memBase;
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mvCtrlModelRevNameGet(name);
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printf("\nSoc: %s", name);
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printf(" (DDR2)\n", name);
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printf("CPU running @ %dMhz L2 running @ %dMhz\n", mvCpuPclkGet()/1000000, mvCpuL2ClkGet()/1000000);
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#ifdef MV_TCLK_CALC
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printf("SysClock = %dMhz , Calc TClock = %dMhz \n\n", CFG_BUS_CLK/1000000, CFG_TCLK/1000000);
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#else
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printf("SysClock = %dMhz , TClock = %dMhz \n\n", CFG_BUS_CLK/1000000, CFG_TCLK/1000000);
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#endif
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#if defined(MV_INC_BOARD_DDIM)
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/* Call dramInit */
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if (0 == (dramTotalSize = initdram(0)))
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{
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printf("DRAM Initialization Failed\n");
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reset_cpu();
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return (1);
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}
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#endif
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mvIntrfaceParamPrint();
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for(i = 0; i< MV_DRAM_MAX_CS; i++)
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{
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#if !defined(MV_88F6082L) && defined(MV_88F6082)
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if (mvCtrlModelRevGet() == MV_6082_A0_ID)
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{
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gd->bd->bi_dram[i].start = (i)?_16M:0;
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gd->bd->bi_dram[i].size = _8M;
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}
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else
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{
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memBase = mvDramIfBankBaseGet(i);
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if (MV_ERROR == memBase)
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gd->bd->bi_dram[i].start = 0;
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else
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gd->bd->bi_dram[i].start = memBase;
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gd->bd->bi_dram[i].size = mvDramIfBankSizeGet(i);
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}
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#else
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memBase = mvDramIfBankBaseGet(i);
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if (MV_ERROR == memBase)
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gd->bd->bi_dram[i].start = 0;
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else
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gd->bd->bi_dram[i].start = memBase;
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gd->bd->bi_dram[i].size = mvDramIfBankSizeGet(i);
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#endif
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dramTotalSize += gd->bd->bi_dram[i].size;
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if (gd->bd->bi_dram[i].size)
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{
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printf("DRAM CS[%d] base 0x%08x ",i, gd->bd->bi_dram[i].start);
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mvSizePrint(gd->bd->bi_dram[i].size);
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printf("\n");
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}
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}
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printf("DRAM Total ");
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mvSizePrint(dramTotalSize);
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mvIntrfaceWidthPrint();
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printf("\n");
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#ifdef MV_INC_DRAM_MFG_TEST
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mvDramMfgTrst();
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#endif
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return 0;
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}
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#if defined(MV_INC_BOARD_DDIM)
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/* u-boot interface function to SDRAM init - this is where all the
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* controlling logic happens */
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long int initdram(int board_type)
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{
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MV_VOIDFUNCPTR pRom;
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MV_U32 forcedCl; /* Forced CAS Latency */
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MV_U32 totalSize;
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char * env;
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MV_TWSI_ADDR slave;
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/* r0 <- current position of code */
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/* test if we run from flash or RAM */
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if(dramBoot != 1)
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{
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slave.type = ADDR7_BIT;
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slave.address = 0;
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mvTwsiInit(CFG_I2C_SPEED, CFG_TCLK, &slave, 0);
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/* Calculating MIN/MAX CAS latency according to user settings */
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env = getenv("CASset");
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if(env && (strcmp(env,"1.5") == 0))
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{
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forcedCl = 15;
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}
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else if(env && (strcmp(env,"2") == 0))
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{
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forcedCl = 20;
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}
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else if(env && (strcmp(env,"2.5") == 0))
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{
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forcedCl = 25;
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}
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else if(env && (strcmp(env,"3") == 0))
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{
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forcedCl = 30;
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}
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else if(env && (strcmp(env,"4") == 0))
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{
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forcedCl = 40;
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}
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else if(env && (strcmp(env,"5") == 0))
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{
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forcedCl = 50;
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}
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else if(env && (strcmp(env,"6") == 0))
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{
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forcedCl = 60;
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}
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else
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{
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forcedCl = 0;
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}
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/* detect the dram configuartion parameters */
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if (MV_OK != mvDramIfDetect(forcedCl,1))
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{
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printf("DRAM Auto Detection Failed! System Halt!\n");
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return 0;
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}
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/* set the dram configuration */
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/* Calculate jump address of _mvDramIfConfig() */
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#if defined(MV_BOOTROM)
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pRom = (MV_VOIDFUNCPTR)(((MV_VOIDFUNCPTR)_mvDramIfConfig - (MV_VOIDFUNCPTR)_start) +
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(MV_VOIDFUNCPTR)CFG_MONITOR_BASE + (MV_VOIDFUNCPTR)MONITOR_HEADER_LEN);
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#else
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pRom = (MV_VOIDFUNCPTR)(((MV_VOIDFUNCPTR)_mvDramIfConfig - (MV_VOIDFUNCPTR)_start) +
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(MV_VOIDFUNCPTR)CFG_MONITOR_BASE);
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#endif
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(*pRom) (); /* Jump to _mvDramIfConfig*/
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}
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totalSize = mvDramIfSizeGet();
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return(totalSize);
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}
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#endif /* #if defined(MV_INC_BOARD_DDIM) */
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#ifdef MV_INC_DRAM_MFG_TEST
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static MV_VOID mvDramMfgTrst(void)
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{
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/* Memory test */
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DECLARE_GLOBAL_DATA_PTR;
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unsigned int mem_len,i,j, pattern;
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unsigned int *mem_start;
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char *env;
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env = getenv("enaPost");
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if(!env || ( (strcmp(env,"Yes") == 0) || (strcmp(env,"yes") == 0) ) )
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{
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printf("Memory test pattern: ");
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for (j = 0 ; j<2 ; j++)
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{
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switch(j){
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case 0:
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pattern=0x55555555;
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printf("0x%X, ",pattern);
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break;
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case 1:
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pattern=0xAAAAAAAA;
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printf("0x%X, ",pattern);
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break;
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default:
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pattern=0x0;
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printf("0x%X, ",pattern);
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break;
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}
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for(i = 0; i< MV_DRAM_MAX_CS; i++)
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{
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mem_start = (unsigned int *)gd->bd->bi_dram[i].start;
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mem_len = gd->bd->bi_dram[i].size;
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if (i == 0)
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{
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mem_start+= _4M;
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mem_len-= _4M;
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}
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mem_len/=4;
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if (MV_OK != mv_mem_test(mem_start, pattern, mem_len))
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{
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printf(" Fail!\n");
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while(1);
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}
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}
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}
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printf(" Pass\n");
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}
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}
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static MV_STATUS mv_mem_test(MV_U32* pMem, MV_U32 pattern, MV_U32 count)
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{
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int i;
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for (i=0 ; i< count ; i+=1)
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*(pMem + i) = pattern;
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if (MV_OK != mv_mem_cmp(pMem, pattern, count))
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{
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return MV_ERROR;
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}
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return MV_OK;
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}
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static MV_STATUS mv_mem_cmp(MV_U32* pMem, MV_U32 pattern, MV_U32 count)
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{
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int i;
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for (i=0 ; i< count ; i+=1)
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{
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if (*(pMem + i) != pattern)
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{
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printf("Fail\n");
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printf("Test failed at 0x%x\n",(pMem + i));
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return MV_ERROR;
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}
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}
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return MV_OK;
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}
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#endif /* MV_INC_DRAM_MFG_TEST */
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