739 lines
22 KiB
C
739 lines
22 KiB
C
/******************************************************************************
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*
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* Author: Xilinx, Inc.
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
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* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
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* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
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* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
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* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
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* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
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* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
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* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
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* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
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* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
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* FITNESS FOR A PARTICULAR PURPOSE.
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*
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*
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* Xilinx hardware products are not intended for use in life support
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* appliances, devices, or systems. Use in such applications is
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* expressly prohibited.
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*
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*
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* (c) Copyright 2002-2004 Xilinx Inc.
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* All rights reserved.
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*
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* FILENAME:
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*
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* xdma_channel.c
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*
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* DESCRIPTION:
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*
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* This file contains the DMA channel component. This component supports
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* a distributed DMA design in which each device can have it's own dedicated
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* DMA channel, as opposed to a centralized DMA design. This component
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* performs processing for DMA on all devices.
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*
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* See xdma_channel.h for more information about this component.
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*
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* NOTES:
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*
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* None.
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*
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******************************************************************************/
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/***************************** Include Files *********************************/
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#include "xdma_channel.h"
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#include "xbasic_types.h"
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#include "xio.h"
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/************************** Constant Definitions *****************************/
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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/************************** Function Prototypes ******************************/
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/******************************************************************************
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*
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* FUNCTION:
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*
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* XDmaChannel_Initialize
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*
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* DESCRIPTION:
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*
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* This function initializes a DMA channel. This function must be called
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* prior to using a DMA channel. Initialization of a channel includes setting
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* up the registers base address, and resetting the channel such that it's in a
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* known state. Interrupts for the channel are disabled when the channel is
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* reset.
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*
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* ARGUMENTS:
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*
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* InstancePtr contains a pointer to the DMA channel to operate on.
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*
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* BaseAddress contains the base address of the registers for the DMA channel.
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*
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* RETURN VALUE:
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*
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* XST_SUCCESS indicating initialization was successful.
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*
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* NOTES:
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*
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* None.
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*
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******************************************************************************/
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XStatus
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XDmaChannel_Initialize(XDmaChannel * InstancePtr, u32 BaseAddress)
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{
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/* assert to verify input arguments, don't assert base address */
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XASSERT_NONVOID(InstancePtr != NULL);
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/* setup the base address of the registers for the DMA channel such
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* that register accesses can be done
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*/
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InstancePtr->RegBaseAddress = BaseAddress;
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/* initialize the scatter gather list such that it indicates it has not
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* been created yet and the DMA channel is ready to use (initialized)
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*/
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InstancePtr->GetPtr = NULL;
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InstancePtr->PutPtr = NULL;
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InstancePtr->CommitPtr = NULL;
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InstancePtr->LastPtr = NULL;
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InstancePtr->TotalDescriptorCount = 0;
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InstancePtr->ActiveDescriptorCount = 0;
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InstancePtr->IsReady = XCOMPONENT_IS_READY;
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/* initialize the version of the component
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*/
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XVersion_FromString(&InstancePtr->Version, (s8 *)"1.00a");
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/* reset the DMA channel such that it's in a known state and ready
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* and indicate the initialization occured with no errors, note that
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* the is ready variable must be set before this call or reset will assert
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*/
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XDmaChannel_Reset(InstancePtr);
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return XST_SUCCESS;
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}
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/******************************************************************************
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*
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* FUNCTION:
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*
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* XDmaChannel_IsReady
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*
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* DESCRIPTION:
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*
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* This function determines if a DMA channel component has been successfully
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* initialized such that it's ready to use.
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*
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* ARGUMENTS:
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*
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* InstancePtr contains a pointer to the DMA channel to operate on.
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*
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* RETURN VALUE:
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*
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* TRUE if the DMA channel component is ready, FALSE otherwise.
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*
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* NOTES:
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*
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* None.
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*
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******************************************************************************/
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u32
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XDmaChannel_IsReady(XDmaChannel * InstancePtr)
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{
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/* assert to verify input arguments used by the base component */
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XASSERT_NONVOID(InstancePtr != NULL);
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return InstancePtr->IsReady == XCOMPONENT_IS_READY;
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}
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/******************************************************************************
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*
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* FUNCTION:
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*
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* XDmaChannel_GetVersion
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*
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* DESCRIPTION:
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*
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* This function gets the software version for the specified DMA channel
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* component.
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*
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* ARGUMENTS:
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*
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* InstancePtr contains a pointer to the DMA channel to operate on.
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*
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* RETURN VALUE:
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*
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* A pointer to the software version of the specified DMA channel.
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*
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* NOTES:
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*
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* None.
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*
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******************************************************************************/
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XVersion *
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XDmaChannel_GetVersion(XDmaChannel * InstancePtr)
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{
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/* assert to verify input arguments */
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XASSERT_NONVOID(InstancePtr != NULL);
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XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
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/* return a pointer to the version of the DMA channel */
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return &InstancePtr->Version;
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}
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/******************************************************************************
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*
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* FUNCTION:
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*
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* XDmaChannel_SelfTest
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*
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* DESCRIPTION:
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*
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* This function performs a self test on the specified DMA channel. This self
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* test is destructive as the DMA channel is reset and a register default is
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* verified.
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*
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* ARGUMENTS:
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*
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* InstancePtr is a pointer to the DMA channel to be operated on.
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*
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* RETURN VALUE:
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*
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* XST_SUCCESS is returned if the self test is successful, or one of the
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* following errors.
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*
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* XST_DMA_RESET_REGISTER_ERROR Indicates the control register value
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* after a reset was not correct
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*
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* NOTES:
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*
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* This test does not performs a DMA transfer to test the channel because the
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* DMA hardware will not currently allow a non-local memory transfer to non-local
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* memory (memory copy), but only allows a non-local memory to or from the device
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* memory (typically a FIFO).
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*
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******************************************************************************/
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#define XDC_CONTROL_REG_RESET_MASK 0x98000000UL /* control reg reset value */
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XStatus
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XDmaChannel_SelfTest(XDmaChannel * InstancePtr)
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{
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u32 ControlReg;
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/* assert to verify input arguments */
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XASSERT_NONVOID(InstancePtr != NULL);
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XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
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/* reset the DMA channel such that it's in a known state before the test
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* it resets to no interrupts enabled, the desired state for the test
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*/
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XDmaChannel_Reset(InstancePtr);
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/* this should be the first test to help prevent a lock up with the polling
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* loop that occurs later in the test, check the reset value of the DMA
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* control register to make sure it's correct, return with an error if not
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*/
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ControlReg = XDmaChannel_GetControl(InstancePtr);
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if (ControlReg != XDC_CONTROL_REG_RESET_MASK) {
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return XST_DMA_RESET_REGISTER_ERROR;
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}
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return XST_SUCCESS;
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}
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/******************************************************************************
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*
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* FUNCTION:
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*
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* XDmaChannel_Reset
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*
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* DESCRIPTION:
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*
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* This function resets the DMA channel. This is a destructive operation such
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* that it should not be done while a channel is being used. If the DMA channel
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* is transferring data into other blocks, such as a FIFO, it may be necessary
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* to reset other blocks. This function does not modify the contents of a
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* scatter gather list for a DMA channel such that the user is responsible for
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* getting buffer descriptors from the list if necessary.
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*
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* ARGUMENTS:
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*
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* InstancePtr contains a pointer to the DMA channel to operate on.
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*
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* RETURN VALUE:
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*
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* None.
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*
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* NOTES:
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*
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* None.
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*
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******************************************************************************/
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void
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XDmaChannel_Reset(XDmaChannel * InstancePtr)
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{
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/* assert to verify input arguments */
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XASSERT_VOID(InstancePtr != NULL);
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XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
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/* reset the DMA channel such that it's in a known state, the reset
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* register is self clearing such that it only has to be set
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*/
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XIo_Out32(InstancePtr->RegBaseAddress + XDC_RST_REG_OFFSET,
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XDC_RESET_MASK);
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}
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/******************************************************************************
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*
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* FUNCTION:
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*
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* XDmaChannel_GetControl
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*
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* DESCRIPTION:
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*
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* This function gets the control register contents of the DMA channel.
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*
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* ARGUMENTS:
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*
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* InstancePtr contains a pointer to the DMA channel to operate on.
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*
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* RETURN VALUE:
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*
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* The control register contents of the DMA channel. One or more of the
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* following values may be contained the register. Each of the values are
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* unique bit masks.
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*
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* XDC_DMACR_SOURCE_INCR_MASK Increment the source address
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* XDC_DMACR_DEST_INCR_MASK Increment the destination address
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* XDC_DMACR_SOURCE_LOCAL_MASK Local source address
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* XDC_DMACR_DEST_LOCAL_MASK Local destination address
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* XDC_DMACR_SG_ENABLE_MASK Scatter gather enable
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* XDC_DMACR_GEN_BD_INTR_MASK Individual buffer descriptor interrupt
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* XDC_DMACR_LAST_BD_MASK Last buffer descriptor in a packet
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*
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* NOTES:
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*
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* None.
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*
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******************************************************************************/
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u32
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XDmaChannel_GetControl(XDmaChannel * InstancePtr)
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{
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/* assert to verify input arguments */
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XASSERT_NONVOID(InstancePtr != NULL);
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XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
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/* return the contents of the DMA control register */
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return XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET);
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}
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/******************************************************************************
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*
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* FUNCTION:
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*
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* XDmaChannel_SetControl
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*
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* DESCRIPTION:
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*
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* This function sets the control register of the specified DMA channel.
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*
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* ARGUMENTS:
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*
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* InstancePtr contains a pointer to the DMA channel to operate on.
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*
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* Control contains the value to be written to the control register of the DMA
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* channel. One or more of the following values may be contained the register.
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* Each of the values are unique bit masks such that they may be ORed together
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* to enable multiple bits or inverted and ANDed to disable multiple bits.
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*
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* XDC_DMACR_SOURCE_INCR_MASK Increment the source address
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* XDC_DMACR_DEST_INCR_MASK Increment the destination address
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* XDC_DMACR_SOURCE_LOCAL_MASK Local source address
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* XDC_DMACR_DEST_LOCAL_MASK Local destination address
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* XDC_DMACR_SG_ENABLE_MASK Scatter gather enable
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* XDC_DMACR_GEN_BD_INTR_MASK Individual buffer descriptor interrupt
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* XDC_DMACR_LAST_BD_MASK Last buffer descriptor in a packet
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*
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* RETURN VALUE:
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*
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* None.
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*
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* NOTES:
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*
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* None.
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*
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******************************************************************************/
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void
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XDmaChannel_SetControl(XDmaChannel * InstancePtr, u32 Control)
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{
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/* assert to verify input arguments except the control which can't be
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* asserted since all values are valid
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*/
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XASSERT_VOID(InstancePtr != NULL);
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XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
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/* set the DMA control register to the specified value */
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XIo_Out32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET, Control);
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}
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/******************************************************************************
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*
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* FUNCTION:
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*
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* XDmaChannel_GetStatus
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*
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* DESCRIPTION:
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*
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* This function gets the status register contents of the DMA channel.
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*
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* ARGUMENTS:
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*
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* InstancePtr contains a pointer to the DMA channel to operate on.
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*
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* RETURN VALUE:
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*
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* The status register contents of the DMA channel. One or more of the
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* following values may be contained the register. Each of the values are
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* unique bit masks.
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*
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* XDC_DMASR_BUSY_MASK The DMA channel is busy
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* XDC_DMASR_BUS_ERROR_MASK A bus error occurred
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* XDC_DMASR_BUS_TIMEOUT_MASK A bus timeout occurred
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* XDC_DMASR_LAST_BD_MASK The last buffer descriptor of a packet
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*
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* NOTES:
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*
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* None.
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*
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******************************************************************************/
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u32
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XDmaChannel_GetStatus(XDmaChannel * InstancePtr)
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{
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/* assert to verify input arguments */
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XASSERT_NONVOID(InstancePtr != NULL);
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XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
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/* return the contents of the DMA status register */
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return XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAS_REG_OFFSET);
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}
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/******************************************************************************
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*
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* FUNCTION:
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*
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* XDmaChannel_SetIntrStatus
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*
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* DESCRIPTION:
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*
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* This function sets the interrupt status register of the specified DMA channel.
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* Setting any bit of the interrupt status register will clear the bit to
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* indicate the interrupt processing has been completed. The definitions of each
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* bit in the register match the definition of the bits in the interrupt enable
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* register.
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*
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* ARGUMENTS:
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*
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* InstancePtr contains a pointer to the DMA channel to operate on.
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*
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* Status contains the value to be written to the status register of the DMA
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* channel. One or more of the following values may be contained the register.
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* Each of the values are unique bit masks such that they may be ORed together
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* to enable multiple bits or inverted and ANDed to disable multiple bits.
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*
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* XDC_IXR_DMA_DONE_MASK The dma operation is done
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* XDC_IXR_DMA_ERROR_MASK The dma operation had an error
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* XDC_IXR_PKT_DONE_MASK A packet is complete
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* XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached
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* XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
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* XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
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* XDC_IXR_BD_MASK A buffer descriptor is done
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*
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* RETURN VALUE:
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*
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* None.
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*
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* NOTES:
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*
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* None.
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*
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******************************************************************************/
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void
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XDmaChannel_SetIntrStatus(XDmaChannel * InstancePtr, u32 Status)
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{
|
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/* assert to verify input arguments except the status which can't be
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* asserted since all values are valid
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*/
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XASSERT_VOID(InstancePtr != NULL);
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XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
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|
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/* set the interrupt status register with the specified value such that
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* all bits which are set in the register are cleared effectively clearing
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* any active interrupts
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*/
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XIo_Out32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET, Status);
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}
|
|
|
|
/******************************************************************************
|
|
*
|
|
* FUNCTION:
|
|
*
|
|
* XDmaChannel_GetIntrStatus
|
|
*
|
|
* DESCRIPTION:
|
|
*
|
|
* This function gets the interrupt status register of the specified DMA channel.
|
|
* The interrupt status register indicates which interrupts are active
|
|
* for the DMA channel. If an interrupt is active, the status register must be
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* set (written) with the bit set for each interrupt which has been processed
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* in order to clear the interrupts. The definitions of each bit in the register
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* match the definition of the bits in the interrupt enable register.
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*
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|
* ARGUMENTS:
|
|
*
|
|
* InstancePtr contains a pointer to the DMA channel to operate on.
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|
*
|
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* RETURN VALUE:
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|
*
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* The interrupt status register contents of the specified DMA channel.
|
|
* One or more of the following values may be contained the register.
|
|
* Each of the values are unique bit masks.
|
|
*
|
|
* XDC_IXR_DMA_DONE_MASK The dma operation is done
|
|
* XDC_IXR_DMA_ERROR_MASK The dma operation had an error
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* XDC_IXR_PKT_DONE_MASK A packet is complete
|
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* XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached
|
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* XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
|
|
* XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
|
|
* XDC_IXR_SG_END_MASK Current descriptor was the end of the list
|
|
* XDC_IXR_BD_MASK A buffer descriptor is done
|
|
*
|
|
* NOTES:
|
|
*
|
|
* None.
|
|
*
|
|
******************************************************************************/
|
|
u32
|
|
XDmaChannel_GetIntrStatus(XDmaChannel * InstancePtr)
|
|
{
|
|
/* assert to verify input arguments */
|
|
|
|
XASSERT_NONVOID(InstancePtr != NULL);
|
|
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
|
|
|
|
/* return the contents of the interrupt status register */
|
|
|
|
return XIo_In32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET);
|
|
}
|
|
|
|
/******************************************************************************
|
|
*
|
|
* FUNCTION:
|
|
*
|
|
* XDmaChannel_SetIntrEnable
|
|
*
|
|
* DESCRIPTION:
|
|
*
|
|
* This function sets the interrupt enable register of the specified DMA
|
|
* channel. The interrupt enable register contains bits which enable
|
|
* individual interrupts for the DMA channel. The definitions of each bit
|
|
* in the register match the definition of the bits in the interrupt status
|
|
* register.
|
|
*
|
|
* ARGUMENTS:
|
|
*
|
|
* InstancePtr contains a pointer to the DMA channel to operate on.
|
|
*
|
|
* Enable contains the interrupt enable register contents to be written
|
|
* in the DMA channel. One or more of the following values may be contained
|
|
* the register. Each of the values are unique bit masks such that they may be
|
|
* ORed together to enable multiple bits or inverted and ANDed to disable
|
|
* multiple bits.
|
|
*
|
|
* XDC_IXR_DMA_DONE_MASK The dma operation is done
|
|
* XDC_IXR_DMA_ERROR_MASK The dma operation had an error
|
|
* XDC_IXR_PKT_DONE_MASK A packet is complete
|
|
* XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached
|
|
* XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
|
|
* XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
|
|
* XDC_IXR_SG_END_MASK Current descriptor was the end of the list
|
|
* XDC_IXR_BD_MASK A buffer descriptor is done
|
|
*
|
|
* RETURN VALUE:
|
|
*
|
|
* None.
|
|
*
|
|
* NOTES:
|
|
*
|
|
* None.
|
|
*
|
|
******************************************************************************/
|
|
void
|
|
XDmaChannel_SetIntrEnable(XDmaChannel * InstancePtr, u32 Enable)
|
|
{
|
|
/* assert to verify input arguments except the enable which can't be
|
|
* asserted since all values are valid
|
|
*/
|
|
XASSERT_VOID(InstancePtr != NULL);
|
|
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
|
|
|
|
/* set the interrupt enable register to the specified value */
|
|
|
|
XIo_Out32(InstancePtr->RegBaseAddress + XDC_IE_REG_OFFSET, Enable);
|
|
}
|
|
|
|
/******************************************************************************
|
|
*
|
|
* FUNCTION:
|
|
*
|
|
* XDmaChannel_GetIntrEnable
|
|
*
|
|
* DESCRIPTION:
|
|
*
|
|
* This function gets the interrupt enable of the DMA channel. The
|
|
* interrupt enable contains flags which enable individual interrupts for the
|
|
* DMA channel. The definitions of each bit in the register match the definition
|
|
* of the bits in the interrupt status register.
|
|
*
|
|
* ARGUMENTS:
|
|
*
|
|
* InstancePtr contains a pointer to the DMA channel to operate on.
|
|
*
|
|
* RETURN VALUE:
|
|
*
|
|
* The interrupt enable of the DMA channel. One or more of the following values
|
|
* may be contained the register. Each of the values are unique bit masks.
|
|
*
|
|
* XDC_IXR_DMA_DONE_MASK The dma operation is done
|
|
* XDC_IXR_DMA_ERROR_MASK The dma operation had an error
|
|
* XDC_IXR_PKT_DONE_MASK A packet is complete
|
|
* XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached
|
|
* XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
|
|
* XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
|
|
* XDC_IXR_BD_MASK A buffer descriptor is done
|
|
*
|
|
* NOTES:
|
|
*
|
|
* None.
|
|
*
|
|
******************************************************************************/
|
|
u32
|
|
XDmaChannel_GetIntrEnable(XDmaChannel * InstancePtr)
|
|
{
|
|
/* assert to verify input arguments */
|
|
|
|
XASSERT_NONVOID(InstancePtr != NULL);
|
|
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
|
|
|
|
/* return the contents of the interrupt enable register */
|
|
|
|
return XIo_In32(InstancePtr->RegBaseAddress + XDC_IE_REG_OFFSET);
|
|
}
|
|
|
|
/******************************************************************************
|
|
*
|
|
* FUNCTION:
|
|
*
|
|
* XDmaChannel_Transfer
|
|
*
|
|
* DESCRIPTION:
|
|
*
|
|
* This function starts the DMA channel transferring data from a memory source
|
|
* to a memory destination. This function only starts the operation and returns
|
|
* before the operation may be complete. If the interrupt is enabled, an
|
|
* interrupt will be generated when the operation is complete, otherwise it is
|
|
* necessary to poll the channel status to determine when it's complete. It is
|
|
* the responsibility of the caller to determine when the operation is complete
|
|
* by handling the generated interrupt or polling the status. It is also the
|
|
* responsibility of the caller to ensure that the DMA channel is not busy with
|
|
* another transfer before calling this function.
|
|
*
|
|
* ARGUMENTS:
|
|
*
|
|
* InstancePtr contains a pointer to the DMA channel to operate on.
|
|
*
|
|
* SourcePtr contains a pointer to the source memory where the data is to
|
|
* be tranferred from and must be 32 bit aligned.
|
|
*
|
|
* DestinationPtr contains a pointer to the destination memory where the data
|
|
* is to be transferred and must be 32 bit aligned.
|
|
*
|
|
* ByteCount contains the number of bytes to transfer during the DMA operation.
|
|
*
|
|
* RETURN VALUE:
|
|
*
|
|
* None.
|
|
*
|
|
* NOTES:
|
|
*
|
|
* The DMA h/w will not currently allow a non-local memory transfer to non-local
|
|
* memory (memory copy), but only allows a non-local memory to or from the device
|
|
* memory (typically a FIFO).
|
|
*
|
|
* It is the responsibility of the caller to ensure that the cache is
|
|
* flushed and invalidated both before and after the DMA operation completes
|
|
* if the memory pointed to is cached. The caller must also ensure that the
|
|
* pointers contain a physical address rather than a virtual address
|
|
* if address translation is being used.
|
|
*
|
|
******************************************************************************/
|
|
void
|
|
XDmaChannel_Transfer(XDmaChannel * InstancePtr,
|
|
u32 * SourcePtr, u32 * DestinationPtr, u32 ByteCount)
|
|
{
|
|
/* assert to verify input arguments and the alignment of any arguments
|
|
* which have expected alignments
|
|
*/
|
|
XASSERT_VOID(InstancePtr != NULL);
|
|
XASSERT_VOID(SourcePtr != NULL);
|
|
XASSERT_VOID(((u32) SourcePtr & 3) == 0);
|
|
XASSERT_VOID(DestinationPtr != NULL);
|
|
XASSERT_VOID(((u32) DestinationPtr & 3) == 0);
|
|
XASSERT_VOID(ByteCount != 0);
|
|
XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
|
|
|
|
/* setup the source and destination address registers for the transfer */
|
|
|
|
XIo_Out32(InstancePtr->RegBaseAddress + XDC_SA_REG_OFFSET,
|
|
(u32) SourcePtr);
|
|
|
|
XIo_Out32(InstancePtr->RegBaseAddress + XDC_DA_REG_OFFSET,
|
|
(u32) DestinationPtr);
|
|
|
|
/* start the DMA transfer to copy from the source buffer to the
|
|
* destination buffer by writing the length to the length register
|
|
*/
|
|
XIo_Out32(InstancePtr->RegBaseAddress + XDC_LEN_REG_OFFSET, ByteCount);
|
|
}
|