403 lines
14 KiB
C
403 lines
14 KiB
C
/******************************************************************************
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*
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* Author: Xilinx, Inc.
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
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* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
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* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
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* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
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* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
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* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
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* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
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* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
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* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
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* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
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* FITNESS FOR A PARTICULAR PURPOSE.
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*
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*
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* Xilinx hardware products are not intended for use in life support
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* appliances, devices, or systems. Use in such applications is
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* expressly prohibited.
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*
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*
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* (c) Copyright 2002-2004 Xilinx Inc.
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* All rights reserved.
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*
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xemac_intr.c
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*
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* This file contains general interrupt-related functions of the XEmac driver.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -----------------------------------------------
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* 1.00a rpm 07/31/01 First release
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* 1.00b rpm 02/20/02 Repartitioned files and functions
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* 1.00c rpm 12/05/02 New version includes support for simple DMA
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* 1.00c rpm 03/31/03 Added comment to indicate that no Receive Length FIFO
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* overrun interrupts occur in v1.00l and later of the EMAC
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* device. This avoids the need to reset the device on
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* receive overruns.
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* </pre>
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*
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******************************************************************************/
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/***************************** Include Files *********************************/
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#include "xbasic_types.h"
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#include "xemac_i.h"
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#include "xio.h"
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#include "xipif_v1_23_b.h" /* Uses v1.23b of the IPIF */
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/************************** Constant Definitions *****************************/
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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/************************** Variable Definitions *****************************/
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/************************** Function Prototypes ******************************/
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/*****************************************************************************/
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/**
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*
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* Set the callback function for handling asynchronous errors. The upper layer
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* software should call this function during initialization.
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*
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* The error callback is invoked by the driver within interrupt context, so it
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* needs to do its job quickly. If there are potentially slow operations within
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* the callback, these should be done at task-level.
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*
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* The Xilinx errors that must be handled by the callback are:
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* - XST_DMA_ERROR indicates an unrecoverable DMA error occurred. This is
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* typically a bus error or bus timeout. The handler must reset and
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* re-configure the device.
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* - XST_FIFO_ERROR indicates an unrecoverable FIFO error occurred. This is a
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* deadlock condition in the packet FIFO. The handler must reset and
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* re-configure the device.
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* - XST_RESET_ERROR indicates an unrecoverable MAC error occurred, usually an
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* overrun or underrun. The handler must reset and re-configure the device.
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* - XST_DMA_SG_NO_LIST indicates an attempt was made to access a scatter-gather
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* DMA list that has not yet been created.
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* - XST_DMA_SG_LIST_EMPTY indicates the driver tried to get a descriptor from
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* the receive descriptor list, but the list was empty.
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*
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* @param InstancePtr is a pointer to the XEmac instance to be worked on.
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* @param CallBackRef is a reference pointer to be passed back to the adapter in
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* the callback. This helps the adapter correlate the callback to a
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* particular driver.
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* @param FuncPtr is the pointer to the callback function.
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*
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* @return
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*
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* None.
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*
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* @note
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*
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* None.
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*
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******************************************************************************/
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void
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XEmac_SetErrorHandler(XEmac * InstancePtr, void *CallBackRef,
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XEmac_ErrorHandler FuncPtr)
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{
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XASSERT_VOID(InstancePtr != NULL);
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XASSERT_VOID(FuncPtr != NULL);
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XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
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InstancePtr->ErrorHandler = FuncPtr;
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InstancePtr->ErrorRef = CallBackRef;
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}
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/****************************************************************************/
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/*
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*
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* Check the interrupt status bits of the Ethernet MAC for errors. Errors
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* currently handled are:
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* - Receive length FIFO overrun. Indicates data was lost due to the receive
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* length FIFO becoming full during the reception of a packet. Only a device
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* reset clears this condition.
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* - Receive length FIFO underrun. An attempt to read an empty FIFO. Only a
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* device reset clears this condition.
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* - Transmit status FIFO overrun. Indicates data was lost due to the transmit
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* status FIFO becoming full following the transmission of a packet. Only a
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* device reset clears this condition.
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* - Transmit status FIFO underrun. An attempt to read an empty FIFO. Only a
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* device reset clears this condition.
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* - Transmit length FIFO overrun. Indicates data was lost due to the transmit
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* length FIFO becoming full following the transmission of a packet. Only a
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* device reset clears this condition.
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* - Transmit length FIFO underrun. An attempt to read an empty FIFO. Only a
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* device reset clears this condition.
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* - Receive data FIFO overrun. Indicates data was lost due to the receive data
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* FIFO becoming full during the reception of a packet.
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* - Receive data errors:
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* - Receive missed frame error. Valid data was lost by the MAC.
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* - Receive collision error. Data was lost by the MAC due to a collision.
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* - Receive FCS error. Data was dicarded by the MAC due to FCS error.
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* - Receive length field error. Data was dicarded by the MAC due to an invalid
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* length field in the packet.
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* - Receive short error. Data was dicarded by the MAC because a packet was
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* shorter than allowed.
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* - Receive long error. Data was dicarded by the MAC because a packet was
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* longer than allowed.
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* - Receive alignment error. Data was truncated by the MAC because its length
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* was not byte-aligned.
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*
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* @param InstancePtr is a pointer to the XEmac instance to be worked on.
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* @param IntrStatus is the contents of the interrupt status register to be checked
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*
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* @return
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*
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* None.
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*
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* @note
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*
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* This function is intended for internal use only.
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*
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******************************************************************************/
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void
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XEmac_CheckEmacError(XEmac * InstancePtr, u32 IntrStatus)
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{
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u32 ResetError = FALSE;
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/*
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* First check for receive fifo overrun/underrun errors. Most require a
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* reset by the user to clear, but the data FIFO overrun error does not.
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*/
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if (IntrStatus & XEM_EIR_RECV_DFIFO_OVER_MASK) {
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InstancePtr->Stats.RecvOverrunErrors++;
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InstancePtr->Stats.FifoErrors++;
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}
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if (IntrStatus & XEM_EIR_RECV_LFIFO_OVER_MASK) {
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/*
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* Receive Length FIFO overrun interrupts no longer occur in v1.00l
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* and later of the EMAC device. Frames are just dropped by the EMAC
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* if the length FIFO is full. The user would notice the Receive Missed
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* Frame count incrementing without any other errors being reported.
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* This code is left here for backward compatibility with v1.00k and
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* older EMAC devices.
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*/
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InstancePtr->Stats.RecvOverrunErrors++;
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InstancePtr->Stats.FifoErrors++;
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ResetError = TRUE; /* requires a reset */
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}
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if (IntrStatus & XEM_EIR_RECV_LFIFO_UNDER_MASK) {
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InstancePtr->Stats.RecvUnderrunErrors++;
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InstancePtr->Stats.FifoErrors++;
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ResetError = TRUE; /* requires a reset */
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}
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/*
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* Now check for general receive errors. Get the latest count where
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* available, otherwise just bump the statistic so we know the interrupt
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* occurred.
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*/
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if (IntrStatus & XEM_EIR_RECV_ERROR_MASK) {
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if (IntrStatus & XEM_EIR_RECV_MISSED_FRAME_MASK) {
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/*
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* Caused by length FIFO or data FIFO overruns on receive side
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*/
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InstancePtr->Stats.RecvMissedFrameErrors =
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XIo_In32(InstancePtr->BaseAddress +
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XEM_RMFC_OFFSET);
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}
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if (IntrStatus & XEM_EIR_RECV_COLLISION_MASK) {
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InstancePtr->Stats.RecvCollisionErrors =
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XIo_In32(InstancePtr->BaseAddress + XEM_RCC_OFFSET);
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}
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if (IntrStatus & XEM_EIR_RECV_FCS_ERROR_MASK) {
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InstancePtr->Stats.RecvFcsErrors =
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XIo_In32(InstancePtr->BaseAddress +
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XEM_RFCSEC_OFFSET);
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}
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if (IntrStatus & XEM_EIR_RECV_LEN_ERROR_MASK) {
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InstancePtr->Stats.RecvLengthFieldErrors++;
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}
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if (IntrStatus & XEM_EIR_RECV_SHORT_ERROR_MASK) {
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InstancePtr->Stats.RecvShortErrors++;
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}
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if (IntrStatus & XEM_EIR_RECV_LONG_ERROR_MASK) {
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InstancePtr->Stats.RecvLongErrors++;
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}
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if (IntrStatus & XEM_EIR_RECV_ALIGN_ERROR_MASK) {
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InstancePtr->Stats.RecvAlignmentErrors =
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XIo_In32(InstancePtr->BaseAddress +
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XEM_RAEC_OFFSET);
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}
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/*
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* Bump recv interrupts stats only if not scatter-gather DMA (this
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* stat gets bumped elsewhere in that case)
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*/
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if (!XEmac_mIsSgDma(InstancePtr)) {
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InstancePtr->Stats.RecvInterrupts++; /* TODO: double bump? */
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}
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}
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/*
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* Check for transmit errors. These apply to both DMA and non-DMA modes
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* of operation. The entire device should be reset after overruns or
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* underruns.
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*/
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if (IntrStatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
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XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
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InstancePtr->Stats.XmitOverrunErrors++;
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InstancePtr->Stats.FifoErrors++;
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ResetError = TRUE;
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}
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if (IntrStatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
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XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
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InstancePtr->Stats.XmitUnderrunErrors++;
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InstancePtr->Stats.FifoErrors++;
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ResetError = TRUE;
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}
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if (ResetError) {
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/*
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* If a reset error occurred, disable the EMAC interrupts since the
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* reset-causing interrupt(s) is latched in the EMAC - meaning it will
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* keep occurring until the device is reset. In order to give the higher
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* layer software time to reset the device, we have to disable the
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* overrun/underrun interrupts until that happens. We trust that the
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* higher layer resets the device. We are able to get away with disabling
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* all EMAC interrupts since the only interrupts it generates are for
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* error conditions, and we don't care about any more errors right now.
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*/
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XIIF_V123B_WRITE_IIER(InstancePtr->BaseAddress, 0);
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/*
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* Invoke the error handler callback, which should result in a reset
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* of the device by the upper layer software.
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*/
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InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
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XST_RESET_ERROR);
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}
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}
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/*****************************************************************************/
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/*
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*
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* Check the receive packet FIFO for errors. FIFO error interrupts are:
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* - Deadlock. See the XPacketFifo component for a description of deadlock on a
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* FIFO.
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*
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* @param InstancePtr is a pointer to the XEmac instance to be worked on.
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*
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* @return
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*
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* Although the function returns void, it can return an asynchronous error to the
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* application through the error handler. It can return XST_FIFO_ERROR if a FIFO
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* error occurred.
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*
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* @note
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*
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* This function is intended for internal use only.
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*
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******************************************************************************/
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void
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XEmac_CheckFifoRecvError(XEmac * InstancePtr)
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{
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/*
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* Although the deadlock is currently the only interrupt from a packet
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* FIFO, make sure it is deadlocked before taking action. There is no
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* need to clear this interrupt since it requires a reset of the device.
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*/
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if (XPF_V100B_IS_DEADLOCKED(&InstancePtr->RecvFifo)) {
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u32 IntrEnable;
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InstancePtr->Stats.FifoErrors++;
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/*
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* Invoke the error callback function, which should result in a reset
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* of the device by the upper layer software. We first need to disable
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* the FIFO interrupt, since otherwise the upper layer thread that
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* handles the reset may never run because this interrupt condition
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* doesn't go away until a reset occurs (there is no way to ack it).
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*/
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IntrEnable = XIIF_V123B_READ_DIER(InstancePtr->BaseAddress);
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XIIF_V123B_WRITE_DIER(InstancePtr->BaseAddress,
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IntrEnable & ~XEM_IPIF_RECV_FIFO_MASK);
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InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
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XST_FIFO_ERROR);
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}
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}
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/*****************************************************************************/
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/*
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*
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* Check the send packet FIFO for errors. FIFO error interrupts are:
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* - Deadlock. See the XPacketFifo component for a description of deadlock on a
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* FIFO.
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*
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* @param InstancePtr is a pointer to the XEmac instance to be worked on.
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*
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* @return
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*
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* Although the function returns void, it can return an asynchronous error to the
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* application through the error handler. It can return XST_FIFO_ERROR if a FIFO
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* error occurred.
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*
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* @note
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*
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* This function is intended for internal use only.
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*
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******************************************************************************/
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void
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XEmac_CheckFifoSendError(XEmac * InstancePtr)
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{
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/*
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* Although the deadlock is currently the only interrupt from a packet
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* FIFO, make sure it is deadlocked before taking action. There is no
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* need to clear this interrupt since it requires a reset of the device.
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*/
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if (XPF_V100B_IS_DEADLOCKED(&InstancePtr->SendFifo)) {
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u32 IntrEnable;
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InstancePtr->Stats.FifoErrors++;
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/*
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* Invoke the error callback function, which should result in a reset
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* of the device by the upper layer software. We first need to disable
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* the FIFO interrupt, since otherwise the upper layer thread that
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* handles the reset may never run because this interrupt condition
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* doesn't go away until a reset occurs (there is no way to ack it).
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*/
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IntrEnable = XIIF_V123B_READ_DIER(InstancePtr->BaseAddress);
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XIIF_V123B_WRITE_DIER(InstancePtr->BaseAddress,
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IntrEnable & ~XEM_IPIF_SEND_FIFO_MASK);
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InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
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XST_FIFO_ERROR);
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}
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}
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