280 lines
10 KiB
C
280 lines
10 KiB
C
/*
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Ported to U-Boot by Christian Pellegrin <chri@ascensit.com>
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Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and
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eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world
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are GPL, so this is, of course, GPL.
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==========================================================================
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dev/dp83902a.h
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National Semiconductor DP83902a ethernet chip
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==========================================================================
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####ECOSGPLCOPYRIGHTBEGIN####
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-------------------------------------------
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This file is part of eCos, the Embedded Configurable Operating System.
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Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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eCos is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 2 or (at your option) any later version.
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eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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You should have received a copy of the GNU General Public License along
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with eCos; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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As a special exception, if other files instantiate templates or use macros
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or inline functions from this file, or you compile this file and link it
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with other works to produce a work based on this file, this file does not
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by itself cause the resulting work to be covered by the GNU General Public
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License. However the source code for this file must still be made available
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in accordance with section (3) of the GNU General Public License.
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This exception does not invalidate any other reasons why a work based on
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this file might be covered by the GNU General Public License.
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Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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at http://sources.redhat.com/ecos/ecos-license/ */
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-------------------------------------------
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####ECOSGPLCOPYRIGHTEND####
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####BSDCOPYRIGHTBEGIN####
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-------------------------------------------
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Portions of this software may have been derived from OpenBSD or other sources,
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and are covered by the appropriate copyright disclaimers included herein.
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-------------------------------------------
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####BSDCOPYRIGHTEND####
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==========================================================================
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#####DESCRIPTIONBEGIN####
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Author(s): gthomas
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Contributors: gthomas, jskov
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Date: 2001-06-13
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Purpose:
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Description:
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####DESCRIPTIONEND####
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==========================================================================
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*/
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/*
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------------------------------------------------------------------------
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Macros for accessing DP registers
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These can be overridden by the platform header
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*/
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#define DP_IN(_b_, _o_, _d_) (_d_) = *( (volatile unsigned char *) ((_b_)+(_o_)))
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#define DP_OUT(_b_, _o_, _d_) *( (volatile unsigned char *) ((_b_)+(_o_))) = (_d_)
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#define DP_IN_DATA(_b_, _d_) (_d_) = *( (volatile unsigned char *) ((_b_)))
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#define DP_OUT_DATA(_b_, _d_) *( (volatile unsigned char *) ((_b_))) = (_d_)
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/* here is all the data */
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#define cyg_uint8 unsigned char
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#define cyg_uint16 unsigned short
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#define bool int
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#define false 0
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#define true 1
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#define CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA 1
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#define CYGACC_CALL_IF_DELAY_US(X) my_udelay(X)
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typedef struct dp83902a_priv_data {
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cyg_uint8* base;
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cyg_uint8* data;
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cyg_uint8* reset;
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int tx_next; /* First free Tx page */
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int tx_int; /* Expecting interrupt from this buffer */
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int rx_next; /* First free Rx page */
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int tx1, tx2; /* Page numbers for Tx buffers */
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unsigned long tx1_key, tx2_key; /* Used to ack when packet sent */
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int tx1_len, tx2_len;
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bool tx_started, running, hardwired_esa;
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cyg_uint8 esa[6];
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void* plf_priv;
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/* Buffer allocation */
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int tx_buf1, tx_buf2;
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int rx_buf_start, rx_buf_end;
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} dp83902a_priv_data_t;
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/*
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------------------------------------------------------------------------
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Some forward declarations
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*/
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static void dp83902a_poll(void);
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/* ------------------------------------------------------------------------ */
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/* Register offsets */
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#define DP_CR 0x00
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#define DP_CLDA0 0x01
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#define DP_PSTART 0x01 /* write */
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#define DP_CLDA1 0x02
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#define DP_PSTOP 0x02 /* write */
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#define DP_BNDRY 0x03
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#define DP_TSR 0x04
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#define DP_TPSR 0x04 /* write */
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#define DP_NCR 0x05
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#define DP_TBCL 0x05 /* write */
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#define DP_FIFO 0x06
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#define DP_TBCH 0x06 /* write */
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#define DP_ISR 0x07
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#define DP_CRDA0 0x08
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#define DP_RSAL 0x08 /* write */
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#define DP_CRDA1 0x09
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#define DP_RSAH 0x09 /* write */
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#define DP_RBCL 0x0a /* write */
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#define DP_RBCH 0x0b /* write */
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#define DP_RSR 0x0c
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#define DP_RCR 0x0c /* write */
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#define DP_FER 0x0d
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#define DP_TCR 0x0d /* write */
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#define DP_CER 0x0e
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#define DP_DCR 0x0e /* write */
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#define DP_MISSED 0x0f
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#define DP_IMR 0x0f /* write */
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#define DP_DATAPORT 0x10 /* "eprom" data port */
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#define DP_P1_CR 0x00
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#define DP_P1_PAR0 0x01
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#define DP_P1_PAR1 0x02
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#define DP_P1_PAR2 0x03
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#define DP_P1_PAR3 0x04
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#define DP_P1_PAR4 0x05
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#define DP_P1_PAR5 0x06
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#define DP_P1_CURP 0x07
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#define DP_P1_MAR0 0x08
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#define DP_P1_MAR1 0x09
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#define DP_P1_MAR2 0x0a
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#define DP_P1_MAR3 0x0b
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#define DP_P1_MAR4 0x0c
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#define DP_P1_MAR5 0x0d
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#define DP_P1_MAR6 0x0e
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#define DP_P1_MAR7 0x0f
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#define DP_P2_CR 0x00
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#define DP_P2_PSTART 0x01
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#define DP_P2_CLDA0 0x01 /* write */
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#define DP_P2_PSTOP 0x02
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#define DP_P2_CLDA1 0x02 /* write */
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#define DP_P2_RNPP 0x03
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#define DP_P2_TPSR 0x04
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#define DP_P2_LNPP 0x05
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#define DP_P2_ACH 0x06
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#define DP_P2_ACL 0x07
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#define DP_P2_RCR 0x0c
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#define DP_P2_TCR 0x0d
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#define DP_P2_DCR 0x0e
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#define DP_P2_IMR 0x0f
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/* Command register - common to all pages */
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#define DP_CR_STOP 0x01 /* Stop: software reset */
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#define DP_CR_START 0x02 /* Start: initialize device */
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#define DP_CR_TXPKT 0x04 /* Transmit packet */
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#define DP_CR_RDMA 0x08 /* Read DMA (recv data from device) */
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#define DP_CR_WDMA 0x10 /* Write DMA (send data to device) */
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#define DP_CR_SEND 0x18 /* Send packet */
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#define DP_CR_NODMA 0x20 /* Remote (or no) DMA */
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#define DP_CR_PAGE0 0x00 /* Page select */
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#define DP_CR_PAGE1 0x40
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#define DP_CR_PAGE2 0x80
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#define DP_CR_PAGEMSK 0x3F /* Used to mask out page bits */
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/* Data configuration register */
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#define DP_DCR_WTS 0x01 /* 1=16 bit word transfers */
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#define DP_DCR_BOS 0x02 /* 1=Little Endian */
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#define DP_DCR_LAS 0x04 /* 1=Single 32 bit DMA mode */
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#define DP_DCR_LS 0x08 /* 1=normal mode, 0=loopback */
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#define DP_DCR_ARM 0x10 /* 0=no send command (program I/O) */
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#define DP_DCR_FIFO_1 0x00 /* FIFO threshold */
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#define DP_DCR_FIFO_2 0x20
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#define DP_DCR_FIFO_4 0x40
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#define DP_DCR_FIFO_6 0x60
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#define DP_DCR_INIT (DP_DCR_LS|DP_DCR_FIFO_4)
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/* Interrupt status register */
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#define DP_ISR_RxP 0x01 /* Packet received */
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#define DP_ISR_TxP 0x02 /* Packet transmitted */
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#define DP_ISR_RxE 0x04 /* Receive error */
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#define DP_ISR_TxE 0x08 /* Transmit error */
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#define DP_ISR_OFLW 0x10 /* Receive overflow */
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#define DP_ISR_CNT 0x20 /* Tally counters need emptying */
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#define DP_ISR_RDC 0x40 /* Remote DMA complete */
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#define DP_ISR_RESET 0x80 /* Device has reset (shutdown, error) */
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/* Interrupt mask register */
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#define DP_IMR_RxP 0x01 /* Packet received */
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#define DP_IMR_TxP 0x02 /* Packet transmitted */
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#define DP_IMR_RxE 0x04 /* Receive error */
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#define DP_IMR_TxE 0x08 /* Transmit error */
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#define DP_IMR_OFLW 0x10 /* Receive overflow */
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#define DP_IMR_CNT 0x20 /* Tall counters need emptying */
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#define DP_IMR_RDC 0x40 /* Remote DMA complete */
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#define DP_IMR_All 0x3F /* Everything but remote DMA */
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/* Receiver control register */
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#define DP_RCR_SEP 0x01 /* Save bad(error) packets */
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#define DP_RCR_AR 0x02 /* Accept runt packets */
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#define DP_RCR_AB 0x04 /* Accept broadcast packets */
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#define DP_RCR_AM 0x08 /* Accept multicast packets */
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#define DP_RCR_PROM 0x10 /* Promiscuous mode */
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#define DP_RCR_MON 0x20 /* Monitor mode - 1=accept no packets */
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/* Receiver status register */
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#define DP_RSR_RxP 0x01 /* Packet received */
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#define DP_RSR_CRC 0x02 /* CRC error */
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#define DP_RSR_FRAME 0x04 /* Framing error */
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#define DP_RSR_FO 0x08 /* FIFO overrun */
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#define DP_RSR_MISS 0x10 /* Missed packet */
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#define DP_RSR_PHY 0x20 /* 0=pad match, 1=mad match */
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#define DP_RSR_DIS 0x40 /* Receiver disabled */
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#define DP_RSR_DFR 0x80 /* Receiver processing deferred */
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/* Transmitter control register */
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#define DP_TCR_NOCRC 0x01 /* 1=inhibit CRC */
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#define DP_TCR_NORMAL 0x00 /* Normal transmitter operation */
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#define DP_TCR_LOCAL 0x02 /* Internal NIC loopback */
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#define DP_TCR_INLOOP 0x04 /* Full internal loopback */
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#define DP_TCR_OUTLOOP 0x08 /* External loopback */
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#define DP_TCR_ATD 0x10 /* Auto transmit disable */
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#define DP_TCR_OFFSET 0x20 /* Collision offset adjust */
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/* Transmit status register */
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#define DP_TSR_TxP 0x01 /* Packet transmitted */
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#define DP_TSR_COL 0x04 /* Collision (at least one) */
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#define DP_TSR_ABT 0x08 /* Aborted because of too many collisions */
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#define DP_TSR_CRS 0x10 /* Lost carrier */
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#define DP_TSR_FU 0x20 /* FIFO underrun */
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#define DP_TSR_CDH 0x40 /* Collision Detect Heartbeat */
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#define DP_TSR_OWC 0x80 /* Collision outside normal window */
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#define IEEE_8023_MAX_FRAME 1518 /* Largest possible ethernet frame */
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#define IEEE_8023_MIN_FRAME 64 /* Smallest possible ethernet frame */
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