659 lines
17 KiB
C
659 lines
17 KiB
C
/*
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* (C) Copyright 2002
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* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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/*
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* Configuration support for Xilinx Spartan3 devices. Based
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* on spartan2.c (Rich Ireland, rireland@enterasys.com).
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*/
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#include <common.h> /* core U-Boot definitions */
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#include <spartan3.h> /* Spartan-II device family */
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#if (CONFIG_FPGA & (CFG_XILINX | CFG_SPARTAN3))
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/* Define FPGA_DEBUG to get debug printf's */
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#ifdef FPGA_DEBUG
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#define PRINTF(fmt,args...) printf (fmt ,##args)
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#else
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#define PRINTF(fmt,args...)
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#endif
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#undef CFG_FPGA_CHECK_BUSY
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#undef CFG_FPGA_PROG_FEEDBACK
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/* Note: The assumption is that we cannot possibly run fast enough to
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* overrun the device (the Slave Parallel mode can free run at 50MHz).
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* If there is a need to operate slower, define CONFIG_FPGA_DELAY in
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* the board config file to slow things down.
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*/
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#ifndef CONFIG_FPGA_DELAY
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#define CONFIG_FPGA_DELAY()
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#endif
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#ifndef CFG_FPGA_WAIT
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#define CFG_FPGA_WAIT CFG_HZ/100 /* 10 ms */
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#endif
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static int Spartan3_sp_load( Xilinx_desc *desc, void *buf, size_t bsize );
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static int Spartan3_sp_dump( Xilinx_desc *desc, void *buf, size_t bsize );
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/* static int Spartan3_sp_info( Xilinx_desc *desc ); */
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static int Spartan3_sp_reloc( Xilinx_desc *desc, ulong reloc_offset );
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static int Spartan3_ss_load( Xilinx_desc *desc, void *buf, size_t bsize );
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static int Spartan3_ss_dump( Xilinx_desc *desc, void *buf, size_t bsize );
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/* static int Spartan3_ss_info( Xilinx_desc *desc ); */
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static int Spartan3_ss_reloc( Xilinx_desc *desc, ulong reloc_offset );
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/* ------------------------------------------------------------------------- */
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/* Spartan-II Generic Implementation */
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int Spartan3_load (Xilinx_desc * desc, void *buf, size_t bsize)
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{
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int ret_val = FPGA_FAIL;
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switch (desc->iface) {
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case slave_serial:
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PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
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ret_val = Spartan3_ss_load (desc, buf, bsize);
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break;
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case slave_parallel:
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PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
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ret_val = Spartan3_sp_load (desc, buf, bsize);
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break;
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default:
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printf ("%s: Unsupported interface type, %d\n",
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__FUNCTION__, desc->iface);
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}
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return ret_val;
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}
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int Spartan3_dump (Xilinx_desc * desc, void *buf, size_t bsize)
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{
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int ret_val = FPGA_FAIL;
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switch (desc->iface) {
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case slave_serial:
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PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
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ret_val = Spartan3_ss_dump (desc, buf, bsize);
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break;
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case slave_parallel:
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PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
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ret_val = Spartan3_sp_dump (desc, buf, bsize);
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break;
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default:
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printf ("%s: Unsupported interface type, %d\n",
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__FUNCTION__, desc->iface);
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}
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return ret_val;
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}
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int Spartan3_info( Xilinx_desc *desc )
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{
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return FPGA_SUCCESS;
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}
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int Spartan3_reloc (Xilinx_desc * desc, ulong reloc_offset)
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{
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int ret_val = FPGA_FAIL; /* assume a failure */
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if (desc->family != Xilinx_Spartan3) {
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printf ("%s: Unsupported family type, %d\n",
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__FUNCTION__, desc->family);
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return FPGA_FAIL;
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} else
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switch (desc->iface) {
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case slave_serial:
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ret_val = Spartan3_ss_reloc (desc, reloc_offset);
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break;
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case slave_parallel:
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ret_val = Spartan3_sp_reloc (desc, reloc_offset);
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break;
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default:
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printf ("%s: Unsupported interface type, %d\n",
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__FUNCTION__, desc->iface);
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}
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return ret_val;
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}
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/* ------------------------------------------------------------------------- */
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/* Spartan-II Slave Parallel Generic Implementation */
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static int Spartan3_sp_load (Xilinx_desc * desc, void *buf, size_t bsize)
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{
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int ret_val = FPGA_FAIL; /* assume the worst */
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Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns;
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PRINTF ("%s: start with interface functions @ 0x%p\n",
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__FUNCTION__, fn);
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if (fn) {
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size_t bytecount = 0;
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unsigned char *data = (unsigned char *) buf;
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int cookie = desc->cookie; /* make a local copy */
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unsigned long ts; /* timestamp */
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PRINTF ("%s: Function Table:\n"
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"ptr:\t0x%p\n"
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"struct: 0x%p\n"
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"pre: 0x%p\n"
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"pgm:\t0x%p\n"
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"init:\t0x%p\n"
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"err:\t0x%p\n"
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"clk:\t0x%p\n"
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"cs:\t0x%p\n"
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"wr:\t0x%p\n"
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"read data:\t0x%p\n"
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"write data:\t0x%p\n"
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"busy:\t0x%p\n"
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"abort:\t0x%p\n",
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"post:\t0x%p\n\n",
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__FUNCTION__, &fn, fn, fn->pre, fn->pgm, fn->init, fn->err,
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fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, fn->busy,
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fn->abort, fn->post);
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/*
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* This code is designed to emulate the "Express Style"
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* Continuous Data Loading in Slave Parallel Mode for
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* the Spartan-II Family.
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*/
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#ifdef CFG_FPGA_PROG_FEEDBACK
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printf ("Loading FPGA Device %d...\n", cookie);
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#endif
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/*
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* Run the pre configuration function if there is one.
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*/
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if (*fn->pre) {
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(*fn->pre) (cookie);
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}
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/* Establish the initial state */
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(*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */
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/* Get ready for the burn */
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CONFIG_FPGA_DELAY ();
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(*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */
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ts = get_timer (0); /* get current time */
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/* Now wait for INIT and BUSY to go high */
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do {
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CONFIG_FPGA_DELAY ();
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if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
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puts ("** Timeout waiting for INIT to clear.\n");
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(*fn->abort) (cookie); /* abort the burn */
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return FPGA_FAIL;
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}
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} while ((*fn->init) (cookie) && (*fn->busy) (cookie));
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(*fn->wr) (TRUE, TRUE, cookie); /* Assert write, commit */
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(*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
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(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
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/* Load the data */
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while (bytecount < bsize) {
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/* XXX - do we check for an Ctrl-C press in here ??? */
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/* XXX - Check the error bit? */
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(*fn->wdata) (data[bytecount++], TRUE, cookie); /* write the data */
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CONFIG_FPGA_DELAY ();
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(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
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CONFIG_FPGA_DELAY ();
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(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
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#ifdef CFG_FPGA_CHECK_BUSY
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ts = get_timer (0); /* get current time */
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while ((*fn->busy) (cookie)) {
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/* XXX - we should have a check in here somewhere to
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* make sure we aren't busy forever... */
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CONFIG_FPGA_DELAY ();
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(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
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CONFIG_FPGA_DELAY ();
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(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
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if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
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puts ("** Timeout waiting for BUSY to clear.\n");
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(*fn->abort) (cookie); /* abort the burn */
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return FPGA_FAIL;
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}
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}
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#endif
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#ifdef CFG_FPGA_PROG_FEEDBACK
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if (bytecount % (bsize / 40) == 0)
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putc ('.'); /* let them know we are alive */
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#endif
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}
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CONFIG_FPGA_DELAY ();
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(*fn->cs) (FALSE, TRUE, cookie); /* Deassert the chip select */
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(*fn->wr) (FALSE, TRUE, cookie); /* Deassert the write pin */
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#ifdef CFG_FPGA_PROG_FEEDBACK
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putc ('\n'); /* terminate the dotted line */
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#endif
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/* now check for done signal */
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ts = get_timer (0); /* get current time */
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ret_val = FPGA_SUCCESS;
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while ((*fn->done) (cookie) == FPGA_FAIL) {
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/* XXX - we should have a check in here somewhere to
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* make sure we aren't busy forever... */
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CONFIG_FPGA_DELAY ();
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(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
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CONFIG_FPGA_DELAY ();
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(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
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if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
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puts ("** Timeout waiting for DONE to clear.\n");
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(*fn->abort) (cookie); /* abort the burn */
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ret_val = FPGA_FAIL;
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break;
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}
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}
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if (ret_val == FPGA_SUCCESS) {
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#ifdef CFG_FPGA_PROG_FEEDBACK
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puts ("Done.\n");
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#endif
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}
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/*
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* Run the post configuration function if there is one.
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*/
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if (*fn->post) {
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(*fn->post) (cookie);
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}
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else {
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#ifdef CFG_FPGA_PROG_FEEDBACK
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puts ("Fail.\n");
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#endif
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}
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} else {
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printf ("%s: NULL Interface function table!\n", __FUNCTION__);
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}
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return ret_val;
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}
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static int Spartan3_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize)
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{
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int ret_val = FPGA_FAIL; /* assume the worst */
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Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns;
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if (fn) {
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unsigned char *data = (unsigned char *) buf;
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size_t bytecount = 0;
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int cookie = desc->cookie; /* make a local copy */
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printf ("Starting Dump of FPGA Device %d...\n", cookie);
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(*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
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(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
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/* dump the data */
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while (bytecount < bsize) {
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/* XXX - do we check for an Ctrl-C press in here ??? */
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(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
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(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
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(*fn->rdata) (&(data[bytecount++]), cookie); /* read the data */
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#ifdef CFG_FPGA_PROG_FEEDBACK
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if (bytecount % (bsize / 40) == 0)
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putc ('.'); /* let them know we are alive */
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#endif
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}
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(*fn->cs) (FALSE, FALSE, cookie); /* Deassert the chip select */
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(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
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(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
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#ifdef CFG_FPGA_PROG_FEEDBACK
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putc ('\n'); /* terminate the dotted line */
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#endif
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puts ("Done.\n");
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/* XXX - checksum the data? */
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} else {
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printf ("%s: NULL Interface function table!\n", __FUNCTION__);
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}
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return ret_val;
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}
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static int Spartan3_sp_reloc (Xilinx_desc * desc, ulong reloc_offset)
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{
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int ret_val = FPGA_FAIL; /* assume the worst */
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Xilinx_Spartan3_Slave_Parallel_fns *fn_r, *fn =
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(Xilinx_Spartan3_Slave_Parallel_fns *) (desc->iface_fns);
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if (fn) {
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ulong addr;
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/* Get the relocated table address */
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addr = (ulong) fn + reloc_offset;
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fn_r = (Xilinx_Spartan3_Slave_Parallel_fns *) addr;
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if (!fn_r->relocated) {
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if (memcmp (fn_r, fn,
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sizeof (Xilinx_Spartan3_Slave_Parallel_fns))
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== 0) {
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/* good copy of the table, fix the descriptor pointer */
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desc->iface_fns = fn_r;
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} else {
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PRINTF ("%s: Invalid function table at 0x%p\n",
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__FUNCTION__, fn_r);
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return FPGA_FAIL;
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}
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PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
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desc);
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addr = (ulong) (fn->pre) + reloc_offset;
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fn_r->pre = (Xilinx_pre_fn) addr;
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addr = (ulong) (fn->pgm) + reloc_offset;
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fn_r->pgm = (Xilinx_pgm_fn) addr;
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addr = (ulong) (fn->init) + reloc_offset;
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fn_r->init = (Xilinx_init_fn) addr;
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addr = (ulong) (fn->done) + reloc_offset;
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fn_r->done = (Xilinx_done_fn) addr;
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addr = (ulong) (fn->clk) + reloc_offset;
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fn_r->clk = (Xilinx_clk_fn) addr;
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addr = (ulong) (fn->err) + reloc_offset;
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fn_r->err = (Xilinx_err_fn) addr;
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addr = (ulong) (fn->cs) + reloc_offset;
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fn_r->cs = (Xilinx_cs_fn) addr;
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addr = (ulong) (fn->wr) + reloc_offset;
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fn_r->wr = (Xilinx_wr_fn) addr;
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addr = (ulong) (fn->rdata) + reloc_offset;
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fn_r->rdata = (Xilinx_rdata_fn) addr;
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addr = (ulong) (fn->wdata) + reloc_offset;
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fn_r->wdata = (Xilinx_wdata_fn) addr;
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addr = (ulong) (fn->busy) + reloc_offset;
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fn_r->busy = (Xilinx_busy_fn) addr;
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addr = (ulong) (fn->abort) + reloc_offset;
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fn_r->abort = (Xilinx_abort_fn) addr;
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addr = (ulong) (fn->post) + reloc_offset;
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fn_r->post = (Xilinx_post_fn) addr;
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fn_r->relocated = TRUE;
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} else {
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/* this table has already been moved */
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/* XXX - should check to see if the descriptor is correct */
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desc->iface_fns = fn_r;
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}
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ret_val = FPGA_SUCCESS;
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} else {
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printf ("%s: NULL Interface function table!\n", __FUNCTION__);
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}
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return ret_val;
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}
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/* ------------------------------------------------------------------------- */
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static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
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{
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int ret_val = FPGA_FAIL; /* assume the worst */
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Xilinx_Spartan3_Slave_Serial_fns *fn = desc->iface_fns;
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int i;
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char val;
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PRINTF ("%s: start with interface functions @ 0x%p\n",
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__FUNCTION__, fn);
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if (fn) {
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size_t bytecount = 0;
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unsigned char *data = (unsigned char *) buf;
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int cookie = desc->cookie; /* make a local copy */
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unsigned long ts; /* timestamp */
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PRINTF ("%s: Function Table:\n"
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"ptr:\t0x%p\n"
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"struct: 0x%p\n"
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"pgm:\t0x%p\n"
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"init:\t0x%p\n"
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"clk:\t0x%p\n"
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"wr:\t0x%p\n"
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"done:\t0x%p\n\n",
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__FUNCTION__, &fn, fn, fn->pgm, fn->init,
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fn->clk, fn->wr, fn->done);
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#ifdef CFG_FPGA_PROG_FEEDBACK
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printf ("Loading FPGA Device %d...\n", cookie);
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#endif
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/*
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* Run the pre configuration function if there is one.
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*/
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if (*fn->pre) {
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(*fn->pre) (cookie);
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}
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/* Establish the initial state */
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(*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */
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/* Wait for INIT state (init low) */
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ts = get_timer (0); /* get current time */
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do {
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CONFIG_FPGA_DELAY ();
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if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
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puts ("** Timeout waiting for INIT to start.\n");
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return FPGA_FAIL;
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}
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} while (!(*fn->init) (cookie));
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/* Get ready for the burn */
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CONFIG_FPGA_DELAY ();
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(*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */
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ts = get_timer (0); /* get current time */
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|
/* Now wait for INIT to go high */
|
|
do {
|
|
CONFIG_FPGA_DELAY ();
|
|
if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
|
|
puts ("** Timeout waiting for INIT to clear.\n");
|
|
return FPGA_FAIL;
|
|
}
|
|
} while ((*fn->init) (cookie));
|
|
|
|
/* Load the data */
|
|
while (bytecount < bsize) {
|
|
|
|
/* Xilinx detects an error if INIT goes low (active)
|
|
while DONE is low (inactive) */
|
|
if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
|
|
puts ("** CRC error during FPGA load.\n");
|
|
return (FPGA_FAIL);
|
|
}
|
|
val = data [bytecount ++];
|
|
i = 8;
|
|
do {
|
|
/* Deassert the clock */
|
|
(*fn->clk) (FALSE, TRUE, cookie);
|
|
CONFIG_FPGA_DELAY ();
|
|
/* Write data */
|
|
(*fn->wr) ((val < 0), TRUE, cookie);
|
|
CONFIG_FPGA_DELAY ();
|
|
/* Assert the clock */
|
|
(*fn->clk) (TRUE, TRUE, cookie);
|
|
CONFIG_FPGA_DELAY ();
|
|
val <<= 1;
|
|
i --;
|
|
} while (i > 0);
|
|
|
|
#ifdef CFG_FPGA_PROG_FEEDBACK
|
|
if (bytecount % (bsize / 40) == 0)
|
|
putc ('.'); /* let them know we are alive */
|
|
#endif
|
|
}
|
|
|
|
CONFIG_FPGA_DELAY ();
|
|
|
|
#ifdef CFG_FPGA_PROG_FEEDBACK
|
|
putc ('\n'); /* terminate the dotted line */
|
|
#endif
|
|
|
|
/* now check for done signal */
|
|
ts = get_timer (0); /* get current time */
|
|
ret_val = FPGA_SUCCESS;
|
|
(*fn->wr) (TRUE, TRUE, cookie);
|
|
|
|
while (! (*fn->done) (cookie)) {
|
|
/* XXX - we should have a check in here somewhere to
|
|
* make sure we aren't busy forever... */
|
|
|
|
CONFIG_FPGA_DELAY ();
|
|
(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
|
|
CONFIG_FPGA_DELAY ();
|
|
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
|
|
|
|
putc ('*');
|
|
|
|
if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
|
|
puts ("** Timeout waiting for DONE to clear.\n");
|
|
ret_val = FPGA_FAIL;
|
|
break;
|
|
}
|
|
}
|
|
putc ('\n'); /* terminate the dotted line */
|
|
|
|
#ifdef CFG_FPGA_PROG_FEEDBACK
|
|
if (ret_val == FPGA_SUCCESS) {
|
|
puts ("Done.\n");
|
|
}
|
|
else {
|
|
puts ("Fail.\n");
|
|
}
|
|
#endif
|
|
|
|
} else {
|
|
printf ("%s: NULL Interface function table!\n", __FUNCTION__);
|
|
}
|
|
|
|
return ret_val;
|
|
}
|
|
|
|
static int Spartan3_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize)
|
|
{
|
|
/* Readback is only available through the Slave Parallel and */
|
|
/* boundary-scan interfaces. */
|
|
printf ("%s: Slave Serial Dumping is unavailable\n",
|
|
__FUNCTION__);
|
|
return FPGA_FAIL;
|
|
}
|
|
|
|
static int Spartan3_ss_reloc (Xilinx_desc * desc, ulong reloc_offset)
|
|
{
|
|
int ret_val = FPGA_FAIL; /* assume the worst */
|
|
Xilinx_Spartan3_Slave_Serial_fns *fn_r, *fn =
|
|
(Xilinx_Spartan3_Slave_Serial_fns *) (desc->iface_fns);
|
|
|
|
if (fn) {
|
|
ulong addr;
|
|
|
|
/* Get the relocated table address */
|
|
addr = (ulong) fn + reloc_offset;
|
|
fn_r = (Xilinx_Spartan3_Slave_Serial_fns *) addr;
|
|
|
|
if (!fn_r->relocated) {
|
|
|
|
if (memcmp (fn_r, fn,
|
|
sizeof (Xilinx_Spartan3_Slave_Serial_fns))
|
|
== 0) {
|
|
/* good copy of the table, fix the descriptor pointer */
|
|
desc->iface_fns = fn_r;
|
|
} else {
|
|
PRINTF ("%s: Invalid function table at 0x%p\n",
|
|
__FUNCTION__, fn_r);
|
|
return FPGA_FAIL;
|
|
}
|
|
|
|
PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
|
|
desc);
|
|
|
|
addr = (ulong) (fn->pre) + reloc_offset;
|
|
fn_r->pre = (Xilinx_pre_fn) addr;
|
|
|
|
addr = (ulong) (fn->pgm) + reloc_offset;
|
|
fn_r->pgm = (Xilinx_pgm_fn) addr;
|
|
|
|
addr = (ulong) (fn->init) + reloc_offset;
|
|
fn_r->init = (Xilinx_init_fn) addr;
|
|
|
|
addr = (ulong) (fn->done) + reloc_offset;
|
|
fn_r->done = (Xilinx_done_fn) addr;
|
|
|
|
addr = (ulong) (fn->clk) + reloc_offset;
|
|
fn_r->clk = (Xilinx_clk_fn) addr;
|
|
|
|
addr = (ulong) (fn->wr) + reloc_offset;
|
|
fn_r->wr = (Xilinx_wr_fn) addr;
|
|
|
|
fn_r->relocated = TRUE;
|
|
|
|
} else {
|
|
/* this table has already been moved */
|
|
/* XXX - should check to see if the descriptor is correct */
|
|
desc->iface_fns = fn_r;
|
|
}
|
|
|
|
ret_val = FPGA_SUCCESS;
|
|
} else {
|
|
printf ("%s: NULL Interface function table!\n", __FUNCTION__);
|
|
}
|
|
|
|
return ret_val;
|
|
|
|
}
|
|
|
|
#endif
|