167 lines
7.2 KiB
C
167 lines
7.2 KiB
C
/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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This software file (the "File") is owned and distributed by Marvell
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International Ltd. and/or its affiliates ("Marvell") under the following
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alternative licensing terms. Once you have made an election to distribute the
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File under one of the following license alternatives, please (i) delete this
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introductory statement regarding license alternatives, (ii) delete the two
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license alternatives that you have not elected to use and (iii) preserve the
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Marvell copyright notice above.
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********************************************************************************
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Marvell Commercial License Option
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If you received this File from Marvell and you have entered into a commercial
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license agreement (a "Commercial License") with Marvell, the File is licensed
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to you under the terms of the applicable Commercial License.
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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********************************************************************************
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Marvell BSD License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File under the following licensing terms.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Marvell nor the names of its contributors may be
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used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#ifndef __INCethphyregsh
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#define __INCethphyregsh
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#include "ctrlEnv/mvCtrlEnvSpec.h"
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/* defines */
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#define ETH_PHY_TIMEOUT 10000
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/* registers offsetes defines */
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#ifdef MV_88W8660
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#define ETH_PHY_SMI_REG (MV_ETH_REG_BASE(0) + 0x6010)
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#else
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#define ETH_PHY_SMI_REG (MV_ETH_REG_BASE(0) + 0x004)
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#endif
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/* SMI register fields (ETH_PHY_SMI_REG) */
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#define ETH_PHY_SMI_DATA_OFFS 0 /* Data */
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#define ETH_PHY_SMI_DATA_MASK (0xffff << ETH_PHY_SMI_DATA_OFFS)
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#define ETH_PHY_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
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#define ETH_PHY_SMI_DEV_ADDR_MASK (0x1f << ETH_PHY_SMI_DEV_ADDR_OFFS)
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#define ETH_PHY_SMI_REG_ADDR_OFFS 21 /* PHY device register address */
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#define ETH_PHY_SMI_REG_ADDR_MASK (0x1f << ETH_PHY_SMI_REG_ADDR_OFFS)
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#define ETH_PHY_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
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#define ETH_PHY_SMI_OPCODE_MASK (3 << ETH_PHY_SMI_OPCODE_OFFS)
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#define ETH_PHY_SMI_OPCODE_WRITE (0 << ETH_PHY_SMI_OPCODE_OFFS)
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#define ETH_PHY_SMI_OPCODE_READ (1 << ETH_PHY_SMI_OPCODE_OFFS)
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#define ETH_PHY_SMI_READ_VALID_BIT 27 /* Read Valid */
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#define ETH_PHY_SMI_READ_VALID_MASK (1 << ETH_PHY_SMI_READ_VALID_BIT)
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#define ETH_PHY_SMI_BUSY_BIT 28 /* Busy */
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#define ETH_PHY_SMI_BUSY_MASK (1 << ETH_PHY_SMI_BUSY_BIT)
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/* PHY registers and bits */
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#define ETH_PHY_CTRL_REG 0
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#define ETH_PHY_STATUS_REG 1
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#define ETH_PHY_AUTONEGO_AD_REG 0x4
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#define ETH_PHY_1000BASE_T_CTRL_REG 9
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#define ETH_PHY_SPEC_STATUS_REG 17
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/* ETH_PHY_CTRL_REG bits */
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#define ETH_PHY_CTRL_SPEED_MSB_BIT 6
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#define ETH_PHY_CTRL_SPEED_MSB_MASK (1 << ETH_PHY_CTRL_SPEED_MSB_BIT)
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#define ETH_PHY_CTRL_COLISION_TEST_BIT 7
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#define ETH_PHY_CTRL_COLISION_TEST_MASK (1 << ETH_PHY_CTRL_COLISION_TEST_BIT)
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#define ETH_PHY_CTRL_DUPLEX_BIT 8
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#define ETH_PHY_CTRL_DUPLEX_MASK (1 << ETH_PHY_CTRL_DUPLEX_BIT)
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#define ETH_PHY_CTRL_AN_RESTART_BIT 9
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#define ETH_PHY_CTRL_AN_RESTART_MASK (1 << ETH_PHY_CTRL_AN_RESTART_BIT)
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#define ETH_PHY_CTRL_ISOLATE_BIT 10
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#define ETH_PHY_CTRL_ISOLATE_MASK (1 << ETH_PHY_CTRL_ISOLATE_BIT)
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#define ETH_PHY_CTRL_POWER_DOWN_BIT 11
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#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
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#define ETH_PHY_CTRL_AN_ENABLE_BIT 12
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#define ETH_PHY_CTRL_AN_ENABLE_MASK (1 << ETH_PHY_CTRL_AN_ENABLE_BIT)
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#define ETH_PHY_CTRL_SPEED_LSB_BIT 13
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#define ETH_PHY_CTRL_SPEED_LSB_MASK (1 << ETH_PHY_CTRL_SPEED_LSB_BIT)
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#define ETH_PHY_CTRL_LOOPBACK_BIT 14
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#define ETH_PHY_CTRL_LOOPBACK_MASK (1 << ETH_PHY_CTRL_LOOPBACK_BIT)
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#define ETH_PHY_CTRL_RESET_BIT 15
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#define ETH_PHY_CTRL_RESET_MASK (1 << ETH_PHY_CTRL_RESET_BIT)
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/* ETH_PHY_STATUS_REG bits */
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#define ETH_PHY_STATUS_AN_DONE_BIT 5
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#define ETH_PHY_STATUS_AN_DONE_MASK (1 << ETH_PHY_STATUS_AN_DONE_BIT)
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/* ETH_PHY_1000BASE_T_CTRL_REG bits */
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#define ETH_PHY_1000BASE_ADVERTISE_OFFSET 8
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#define ETH_PHY_1000BASE_ADVERTISE_MASK (0x3 << ETH_PHY_1000BASE_ADVERTISE_OFFSET)
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/* ETH_PHY_SPEC_STATUS_REG bits */
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#define ETH_PHY_SPEC_STATUS_SPEED_OFFS 14
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#define ETH_PHY_SPEC_STATUS_SPEED_MASK (0x3 << ETH_PHY_SPEC_STATUS_SPEED_OFFS)
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#define ETH_PHY_SPEC_STATUS_SPEED_10MBPS (0x0 << ETH_PHY_SPEC_STATUS_SPEED_OFFS)
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#define ETH_PHY_SPEC_STATUS_SPEED_100MBPS (0x1 << ETH_PHY_SPEC_STATUS_SPEED_OFFS)
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#define ETH_PHY_SPEC_STATUS_SPEED_1000MBPS (0x2 << ETH_PHY_SPEC_STATUS_SPEED_OFFS)
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#define ETH_PHY_SPEC_STATUS_DUPLEX_BIT 13
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#define ETH_PHY_SPEC_STATUS_DUPLEX_MASK (0x1 << ETH_PHY_SPEC_STATUS_DUPLEX_BIT)
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#define ETH_PHY_SPEC_STATUS_LINK_BIT 10
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#define ETH_PHY_SPEC_STATUS_LINK_MASK (0x1 << ETH_PHY_SPEC_STATUS_LINK_BIT)
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/* ETH_PHY_SPEC_STATUS_REG bits */
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#define ETH_PHY_LED_ACT_LNK_DV 0x4109
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#endif /* __INCethphyregsh */
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