989 lines
33 KiB
ArmAsm
989 lines
33 KiB
ArmAsm
/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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This software file (the "File") is owned and distributed by Marvell
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International Ltd. and/or its affiliates ("Marvell") under the following
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alternative licensing terms. Once you have made an election to distribute the
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File under one of the following license alternatives, please (i) delete this
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introductory statement regarding license alternatives, (ii) delete the two
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license alternatives that you have not elected to use and (iii) preserve the
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Marvell copyright notice above.
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********************************************************************************
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Marvell Commercial License Option
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If you received this File from Marvell and you have entered into a commercial
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license agreement (a "Commercial License") with Marvell, the File is licensed
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to you under the terms of the applicable Commercial License.
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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********************************************************************************
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Marvell BSD License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File under the following licensing terms.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Marvell nor the names of its contributors may be
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used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#define MV_ASMLANGUAGE
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#include "mvSysHwConfig.h"
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#include "mvOsAsm.h"
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#include "mvBoardEnvSpec.h"
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#include "mvCpuIfRegs.h"
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#include "mvDramIfConfig.h"
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#include "mvDramIfRegs.h"
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#include "pex/mvPexRegs.h"
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#include "pci/mvPciRegs.h"
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#include "mvCtrlEnvSpec.h"
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#include "mvCtrlEnvAsm.h"
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#include "cpu/mvCpuArm.h"
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#include "mvCommon.h"
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/* defines */
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#if !defined(MV_INC_BOARD_DDIM)
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.globl dramBoot1
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dramBoot1:
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.word 0
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/******************************************************************************
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*
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*
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*
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*
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*******************************************************************************/
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#if defined(DB_PRPMC) || defined(DB_PEX_PCI) || defined(DB_MNG)
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/* PEX_PCI and PRPMC boards 256 MB*/
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#define STATIC_SDRAM0_BANK0_SIZE 0x0fff0001
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#define STATIC_SDRAM_CONFIG 0x03248400
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#define STATIC_SDRAM_MODE 0x62
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#define STATIC_DUNIT_CTRL_LOW 0x4041000
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#define STATIC_SDRAM_ADDR_CTRL 0x00000020
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#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220
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#define STATIC_SDRAM_TIME_CTRL_HI 0x0000030F
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#define STATIC_SDRAM_ODT_CTRL_LOW 0x0
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#define STATIC_SDRAM_ODT_CTRL_HI 0x0
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#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0
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#define STATIC_SDRAM_EXT_MODE 0x0
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#elif defined(DB_FPGA)
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/* FPGA DC boards 256 MB*/
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#define STATIC_SDRAM0_BANK0_SIZE 0x0fff0001
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#define STATIC_SDRAM_CONFIG 0x03208400 /* 32bit */
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#define STATIC_SDRAM_MODE 0x22
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#define STATIC_DUNIT_CTRL_LOW 0x03041000
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#define STATIC_SDRAM_ADDR_CTRL 0x00000020
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#define STATIC_SDRAM_TIME_CTRL_LOW 0x11112220
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#define STATIC_SDRAM_TIME_CTRL_HI 0x0000000D
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#define STATIC_SDRAM_ODT_CTRL_LOW 0x0
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#define STATIC_SDRAM_ODT_CTRL_HI 0x0
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#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0
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#define STATIC_SDRAM_EXT_MODE 0x1
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#elif defined(RD_88F6183GP) || defined(DB_CUSTOMER)
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/* Customer 1 DDR2 2 devices 512Mbit by 16 bit */
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#define STATIC_SDRAM0_BANK0_SIZE 0x07ff0001
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#define STATIC_SDRAM_CONFIG 0x03158400
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#define STATIC_SDRAM_MODE 0x452
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#define STATIC_DUNIT_CTRL_LOW 0x06041000
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#define STATIC_SDRAM_ADDR_CTRL 0x00000020
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#define STATIC_SDRAM_TIME_CTRL_LOW 0x11912220
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#define STATIC_SDRAM_TIME_CTRL_HI 0x00000502
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#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000
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#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002
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#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000601
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#define STATIC_SDRAM_EXT_MODE 0x00000440
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#elif defined(RD_88F6183AP)
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/* DDR2 1 devices 512Mbit by 16 bit */
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#define STATIC_SDRAM0_BANK0_SIZE 0x03ff0001
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#define STATIC_SDRAM_CONFIG 0x1f154400
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#define STATIC_SDRAM_MODE 0x432
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#define STATIC_DUNIT_CTRL_LOW 0x04041000
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#define STATIC_SDRAM_ADDR_CTRL 0x00000020
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#define STATIC_SDRAM_TIME_CTRL_LOW 0x11912220
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#define STATIC_SDRAM_TIME_CTRL_HI 0x00000502
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#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000
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#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002
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#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000601
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#define STATIC_SDRAM_EXT_MODE 0x00000440
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/* 6082L MARVELL DIMM */
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#elif defined(DB_88F6082LBP)
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#define STATIC_SDRAM0_BANK0_SIZE 0x07ff0001
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#define STATIC_SDRAM_CONFIG 0x7f158400
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#define STATIC_SDRAM_MODE 0x432
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#define STATIC_DUNIT_CTRL_LOW 0x04041040
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#define STATIC_SDRAM_ADDR_CTRL 0x00000020
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#define STATIC_SDRAM_TIME_CTRL_LOW 0x11612220
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#define STATIC_SDRAM_TIME_CTRL_HI 0x00000501
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#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000
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#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002
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#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000a01
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#define STATIC_SDRAM_EXT_MODE 0x00000440
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#elif defined(RD_88W8660_AP82S)
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/* Shark RD */
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#if defined(MV_DRAM_32M)
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#define STATIC_SDRAM0_BANK0_SIZE 0x01ff0001
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#define STATIC_SDRAM_ADDR_CTRL 0x00000010
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#elif defined(MV_DRAM_16M)
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#define STATIC_SDRAM0_BANK0_SIZE 0x00ff0001
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#define STATIC_SDRAM_ADDR_CTRL 0x00000000
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#else
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#error "NO DDR size selected"
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#endif
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#define STATIC_SDRAM_CONFIG 0x03144400
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#define STATIC_SDRAM_MODE 0x62
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#define STATIC_DUNIT_CTRL_LOW 0x4041000
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#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220
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#define STATIC_SDRAM_TIME_CTRL_HI 0x0000040b
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#define STATIC_SDRAM_ODT_CTRL_LOW 0x0
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#define STATIC_SDRAM_ODT_CTRL_HI 0x0
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#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0
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#define STATIC_SDRAM_EXT_MODE 0x0
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#elif defined(RD_88W8660)
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/* Shark RD */
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#define STATIC_SDRAM0_BANK0_SIZE 0x03ff0001
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#define STATIC_SDRAM_CONFIG 0x03144400
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#define STATIC_SDRAM_MODE 0x62
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#define STATIC_DUNIT_CTRL_LOW 0x4041000
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#define STATIC_SDRAM_ADDR_CTRL 0x00000010
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#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220
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#define STATIC_SDRAM_TIME_CTRL_HI 0x0000040b
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#define STATIC_SDRAM_ODT_CTRL_LOW 0x0
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#define STATIC_SDRAM_ODT_CTRL_HI 0x0
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#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0
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#define STATIC_SDRAM_EXT_MODE 0x0
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#else /* NAS */
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#if defined(RD_88F5182)
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#if defined(MV_88F5082)
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#define STATIC_SDRAM0_BANK0_SIZE 0x3ff0001
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#define STATIC_SDRAM_ADDR_CTRL 0x20
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#else
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#define STATIC_SDRAM0_BANK0_SIZE 0x7ff0001
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#define STATIC_SDRAM_ADDR_CTRL 0x20
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#endif
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#elif defined(RD_88F5182_3)
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#if defined(MV_88F5082)
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#define STATIC_SDRAM0_BANK0_SIZE 0x3ff0001
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#define STATIC_SDRAM_ADDR_CTRL 0x20
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#else
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#define STATIC_SDRAM0_BANK0_SIZE 0x7ff0001
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#define STATIC_SDRAM_ADDR_CTRL 0x20
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#endif
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#else
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#define STATIC_SDRAM0_BANK0_SIZE 0x1ff0001
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#define STATIC_SDRAM_ADDR_CTRL 0x0
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#endif
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#if defined(MV_88F5082)
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#define STATIC_SDRAM_CONFIG 0x3144400
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#else
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#define STATIC_SDRAM_CONFIG 0x3148400
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#endif
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#define STATIC_SDRAM_MODE 0x62
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#define STATIC_DUNIT_CTRL_LOW 0x4041000
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#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220
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#define STATIC_SDRAM_TIME_CTRL_HI 0x40c
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#define STATIC_SDRAM_ODT_CTRL_LOW 0x0
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#define STATIC_SDRAM_ODT_CTRL_HI 0x0
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#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0
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#define STATIC_SDRAM_EXT_MODE 0x0
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#endif
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.globl _mvDramIfStaticInit
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_mvDramIfStaticInit:
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mov r11, LR /* Save link register */
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mov r10, r2
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/* If we boot from NAND jump to DRAM sddress */
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mov r5, #1
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ldr r6, =dramBoot1
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str r5, [r6] /* We started executing from DRAM */
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ldr r6, dramBoot1
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cmp r6, #0
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bne 1f
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/* set all dram windows to 0 */
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mov r6, #0
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MV_REG_WRITE_ASM(r6, r5, 0x1504)
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MV_REG_WRITE_ASM(r6, r5, 0x150c)
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MV_REG_WRITE_ASM(r6, r5, 0x1514)
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MV_REG_WRITE_ASM(r6, r5, 0x151c)
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/* set all dram configuration in temp registers */
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ldr r6, = STATIC_SDRAM0_BANK0_SIZE
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MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG0)
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ldr r6, = STATIC_SDRAM_CONFIG
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MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG1)
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ldr r6, = STATIC_SDRAM_MODE
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MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG2)
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ldr r6, = STATIC_DUNIT_CTRL_LOW
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MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG3)
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ldr r6, = STATIC_SDRAM_ADDR_CTRL
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MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG4)
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ldr r6, = STATIC_SDRAM_TIME_CTRL_LOW
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MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG5)
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ldr r6, = STATIC_SDRAM_TIME_CTRL_HI
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MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6)
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ldr r6, = STATIC_SDRAM_ODT_CTRL_LOW
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MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG7)
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ldr r6, = STATIC_SDRAM_ODT_CTRL_HI
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MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG8)
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ldr r6, = STATIC_SDRAM_DUNIT_ODT_CTRL
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MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG9)
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ldr r6, = STATIC_SDRAM_EXT_MODE
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MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG10)
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mov sp, #0
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bl _mvDramIfConfig
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1:
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mov r2, r10
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mov PC, r11 /* r11 is saved link register */
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#else /* #if !defined(MV_INC_BOARD_DDIM) */
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.globl dramBoot1
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dramBoot1:
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.word 0
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/*******************************************************************************
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* mvDramIfBasicInit - Basic initialization of DRAM interface
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*
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* DESCRIPTION:
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* The function will initialize the DRAM for basic usage. The function
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* will use the TWSI assembly API to extract DIMM parameters according
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* to which DRAM interface will be initialized.
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* The function referes to the following DRAM parameters:
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* 1) DIMM is registered or not.
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* 2) DIMM width detection.
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* 3) DIMM density.
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*
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* INPUT:
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* r3 - required size for initial DRAM.
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*
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* OUTPUT:
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* None.
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*
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* RETURN:
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* None.
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*
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* Note:
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* r4 holds I2C EEPROM address
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* r5 holds SDRAM register base address
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* r7 holds returned values
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* r8 holds SDRAM various configuration registers value.
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* r11 holds return function address.
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*******************************************************************************/
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/* Setting the offsets of the I2C registers */
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#define NUM_OF_ROWS_OFFSET 3
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#define NUM_OF_COLS_OFFSET 4
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#define NUM_OF_RANKS 5
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#define SDRAM_WIDTH_OFFSET 13
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#define NUM_OF_BANKS_OFFSET 17
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#define SUPPORTED_CL_OFFSET 18
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#define DIMM_TYPE_INFO_OFFSET 20 /* DDR2 only */
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#define SDRAM_MODULES_ATTR_OFFSET 21
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#define DRAM_DEV_DENSITY_128M 0x080
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#define DRAM_DEV_DENSITY_256M 0x100
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#define DRAM_DEV_DENSITY_512M 0x200
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.globl _mvDramIfBasicInit
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.extern _i2cInit
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_mvDramIfBasicInit:
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mov r11, LR /* Save link register */
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mov r5, #1
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ldr r8, =dramBoot1
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str r5, [r8] /* We started executing from DRAM */
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/* If we boot from NAND jump to DRAM sddress */
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ldr r8, dramBoot1
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cmp r8, #0
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movne pc, r11
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bl _i2cInit /* Initialize TWSI master */
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/* Get default SDRAM Config values */
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MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG)
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bic r8, r8, #SDRAM_DCFG_MASK
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/* Read device ID */
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MV_CTRL_MODEL_GET_ASM(r4, r5);
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/* Return if OrionN */
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ldr r5, =MV_5180_DEV_ID
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cmp r4, r5
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beq cat_through_end
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/* Return if Orion1 */
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ldr r5, =MV_5181_DEV_ID
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cmp r4, r5
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beq cat_through_end
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/* Return if Nas */
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ldr r5, =MV_5182_DEV_ID
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cmp r4, r5
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beq cat_through_end
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/* Return if Shark */
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ldr r5, =MV_8660_DEV_ID
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cmp r4, r5
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beq cat_through_end
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/* goto calcConfigReg if bigger than Orion2*/
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ldr r5, =MV_5281_DEV_ID
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cmp r4, r5
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bne cat_through
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cat_through:
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/* set cat through - for better performance - in orion2 b0 and higher*/
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orr r8, r8, #SDRAM_CATTHR_EN
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cat_through_end:
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/* Get registered/non registered info from DIMM */
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bl _is_Registered
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beq nonRegistered
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setRegistered:
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orr r8, r8, #SDRAM_REGISTERED /* Set registered bit(17) */
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nonRegistered:
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/* Get SDRAM width */
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bl _get_width
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orr r6, r8, #SDRAM_DCFG_X16_DEV /* x16 devices */
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cmp r7, #16
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beq setConfigReg
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orr r6, r8, #SDRAM_DCFG_X8_DEV /* x8 devices */
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cmp r7, #8
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beq setConfigReg
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/* This is an error. return */
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b exit_ddrAutoConfig
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setConfigReg:
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mov r8, r6
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ldr r6, =SDRAM_CONFIG_DV
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orr r8, r8, r6 /* Add default settings */
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mov r6, r8 /* Do not swap r8 content */
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MV_REG_WRITE_ASM (r6, r5, SDRAM_CONFIG_REG)
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/* Set maximum CL supported by DIMM */
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bl _get_CAL
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/* r7 is DIMM supported CAS (e.g: 3 --> 0x1C) */
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clz r6, r7
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rsb r6, r6, #31 /* r6 = the bit number of MAX CAS supported */
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/* Check the DDR version */
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tst r8, #SDRAM_DTYPE_DDR2
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bne casDdr2
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casDdr1:
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ldr r7, =3 /* stBurstDel field value */
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ldr r8, =0x52 /* Assuming MAX CL = 1.5 */
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cmp r6, #1 /* If CL = 1.5 break */
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beq setModeReg
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ldr r7, =3 /* stBurstDel field value */
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ldr r8, =0x22 /* Assuming MAX CL = 2 */
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cmp r6, #2 /* If CL = 2 break */
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beq setModeReg
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ldr r7, =4 /* stBurstDel field value */
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ldr r8, =0x62 /* Assuming MAX CL = 2.5 */
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cmp r6, #3 /* If CL = 2.5 break */
|
|
beq setModeReg
|
|
|
|
ldr r7, =4 /* stBurstDel field value */
|
|
ldr r8, =0x32 /* Assuming MAX CL = 3 */
|
|
cmp r6, #4 /* If CL = 3 break */
|
|
beq setModeReg
|
|
|
|
ldr r7, =5 /* stBurstDel field value */
|
|
ldr r8, =0x42 /* Assuming MAX CL = 4 */
|
|
cmp r6, #6 /* If CL = 4 break */
|
|
b setModeReg
|
|
|
|
b exit_ddrAutoConfig /* This is an error !! */
|
|
|
|
casDdr2:
|
|
ldr r7, =4 /* stBurstDel field value */
|
|
ldr r8, =0x32 /* Assuming MAX CL = 3 */
|
|
cmp r6, #3 /* If CL = 3 break */
|
|
beq casDdr2Cont
|
|
|
|
ldr r7, =5 /* stBurstDel field value */
|
|
ldr r8, =0x42 /* Assuming MAX CL = 4 */
|
|
cmp r6, #4 /* If CL = 4 break */
|
|
beq casDdr2Cont
|
|
|
|
/* CL 5 currently unsupported. We use CL 4 instead */
|
|
ldr r7, =5 /* stBurstDel field value */
|
|
ldr r8, =0x42 /* Assuming MAX CL = 5 */
|
|
cmp r6, #5 /* If CL = 5 break */
|
|
beq casDdr2Cont
|
|
|
|
b exit_ddrAutoConfig /* This is an error !! */
|
|
casDdr2Cont:
|
|
/* Write recovery for auto-precharge relevant only in DDR2 */
|
|
orr r8, r8, #0x400 /* Default value */
|
|
|
|
setModeReg:
|
|
/* The CPU must not attempt to change the SDRAM Mode register setting */
|
|
/* prior to DRAM controller completion of the DRAM initialization */
|
|
/* sequence. To guarantee this restriction, it is recommended that */
|
|
/* the CPU sets the SDRAM Operation register to NOP command, performs */
|
|
/* read polling until the register is back in Normal operation value, */
|
|
/* and then sets SDRAM Mode register to it's new value. */
|
|
|
|
/* write 'nop' to SDRAM operation */
|
|
mov r6, #0x5 /* 'NOP' command */
|
|
MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG)
|
|
|
|
/* poll SDRAM operation. Make sure its back to normal operation */
|
|
_sdramOpPoll1:
|
|
ldr r6, [r5]
|
|
cmp r6, #0 /* '0' = Normal SDRAM Mode */
|
|
bne _sdramOpPoll1
|
|
|
|
/* Now its safe to write new value to SDRAM Mode register */
|
|
MV_REG_WRITE_ASM (r8, r5, SDRAM_MODE_REG)
|
|
|
|
/* Make the Dunit write the DRAM its new mode */
|
|
mov r6, #0x3 /* Mode Register Set command */
|
|
MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG)
|
|
|
|
/* poll SDRAM operation. Make sure its back to normal operation */
|
|
_sdramOpPoll2:
|
|
ldr r6, [r5]
|
|
cmp r6, #0 /* '0' = Normal SDRAM Mode */
|
|
bne _sdramOpPoll2
|
|
|
|
/* Set Dunit control register according to max CL detected */
|
|
/* If we use registered DIMM, add 1 to stBurstDel */
|
|
MV_REG_READ_ASM (r6, r5, SDRAM_CONFIG_REG)
|
|
tst r6, #SDRAM_REGISTERED
|
|
beq setDunitReg
|
|
add r7, r7, #1
|
|
|
|
setDunitReg:
|
|
ldr r6, =SDRAM_DUNIT_CTRL_LOW_DV
|
|
orr r6, r6, r7, LSL #SDRAM_ST_BURST_DEL_OFFS
|
|
MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG)
|
|
|
|
|
|
/* DIMM density configuration*/
|
|
/* Density = (1 << (rowNum + colNum)) * dramWidth * dramBankNum */
|
|
Density:
|
|
bl _getDensity
|
|
mov r8, r7
|
|
mov r8, r8, LSR #20 /* Move density 20 bits to the right */
|
|
/* For example 0x10000000 --> 0x1000 */
|
|
|
|
mov r6, #0x00
|
|
cmp r8, #DRAM_DEV_DENSITY_128M
|
|
beq densCont
|
|
|
|
mov r6, #0x10
|
|
cmp r8, #DRAM_DEV_DENSITY_256M
|
|
beq densCont
|
|
|
|
mov r6, #0x20
|
|
cmp r8, #DRAM_DEV_DENSITY_512M
|
|
beq densCont
|
|
|
|
/* This is an error. return */
|
|
b exit_ddrAutoConfig
|
|
|
|
densCont:
|
|
MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_REG)
|
|
|
|
/* Config DDR2 registers (Extended mode, ODTs and pad calibration) */
|
|
MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG)
|
|
tst r8, #SDRAM_DTYPE_DDR2
|
|
beq _extModeODTEnd
|
|
|
|
|
|
/* Set DDR Extended Mode register for working with CS[0] */
|
|
/* write 'nop' to SDRAM operation */
|
|
mov r6, #0x5 /* 'NOP' command */
|
|
MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG)
|
|
|
|
/* poll SDRAM operation. Make sure its back to normal operation */
|
|
_sdramOpPoll3:
|
|
ldr r6, [r5]
|
|
cmp r6, #0 /* '0' = Normal SDRAM Mode */
|
|
bne _sdramOpPoll3
|
|
|
|
/* Now its safe to write new value to SDRAM Extended Mode register */
|
|
ldr r6, =DDR_SDRAM_EXT_MODE_CS0_DV
|
|
MV_REG_WRITE_ASM (r6, r5, SDRAM_EXTENDED_MODE_REG)
|
|
|
|
/* Make the Dunit write the DRAM its new extended mode */
|
|
mov r6, #0x4 /* Extended Mode Register Set command */
|
|
MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG)
|
|
|
|
/* poll SDRAM operation. Make sure its back to normal operation */
|
|
_sdramOpPoll4:
|
|
ldr r6, [r5]
|
|
cmp r6, #0 /* '0' = Normal SDRAM Mode */
|
|
bne _sdramOpPoll4
|
|
|
|
/* ODT configuration is done for single bank CS[0] only */
|
|
/* Config DDR2 On Die Termination (ODT) registers */
|
|
ldr r6, =DDR2_ODT_CTRL_LOW_CS0_DV
|
|
MV_REG_WRITE_ASM (r6, r5, DDR2_SDRAM_ODT_CTRL_LOW_REG)
|
|
|
|
ldr r6, =DDR2_ODT_CTRL_HIGH_CS0_DV
|
|
MV_REG_WRITE_ASM (r6, r5, DDR2_SDRAM_ODT_CTRL_HIGH_REG)
|
|
|
|
ldr r6, =DDR2_DUNIT_ODT_CTRL_CS0_DV
|
|
MV_REG_WRITE_ASM (r6, r5, DDR2_DUNIT_ODT_CONTROL_REG)
|
|
|
|
|
|
/* we will check what device we are running and perform
|
|
Initialization according to device value */
|
|
|
|
_extModeODTEnd:
|
|
|
|
/* Implement Guideline (GL# MEM-2) P_CAL Automatic Calibration */
|
|
/* Does Not Work for Address/Control and Data Pads. */
|
|
/* Relevant for: 88F5181-A1/B0 and 88F5281-A0 */
|
|
|
|
/* Read device ID */
|
|
MV_CTRL_MODEL_GET_ASM(r6, r5);
|
|
/* Read device revision */
|
|
MV_CTRL_REV_GET_ASM(r8, r5);
|
|
|
|
/* Continue if OrionN */
|
|
ldr r5, =MV_5180_DEV_ID
|
|
cmp r6, r5
|
|
bne 1f
|
|
b glMem2End
|
|
1:
|
|
|
|
/* Continue if Orion1 and device revision B1 */
|
|
ldr r5, =MV_5181_DEV_ID
|
|
cmp r6, r5
|
|
bne 1f
|
|
|
|
cmp r8, #MV_5181_B1_REV
|
|
bge glMem2End
|
|
b glMem2Start
|
|
1:
|
|
|
|
/* Orion NAS */
|
|
ldr r5, =MV_5182_DEV_ID
|
|
cmp r6, r5
|
|
beq glMem2Start
|
|
|
|
/* Orion Shark */
|
|
ldr r5, =MV_8660_DEV_ID
|
|
cmp r6, r5
|
|
beq glMem2Start
|
|
|
|
b glMem2End
|
|
|
|
glMem2Start:
|
|
|
|
/* DDR SDRAM Address/Control Pads Calibration */
|
|
MV_REG_READ_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG)
|
|
|
|
/* Set Bit [31] to make the register writable */
|
|
orr r8, r6, #SDRAM_WR_EN
|
|
|
|
MV_REG_WRITE_ASM (r8, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG)
|
|
|
|
bic r6, r6, #SDRAM_WR_EN /* Make register read-only */
|
|
bic r6, r6, #SDRAM_TUNE_EN /* Disable auto calibration */
|
|
bic r6, r6, #SDRAM_DRVN_MASK /* Clear r5[5:0]<DrvN> */
|
|
bic r6, r6, #SDRAM_DRVP_MASK /* Clear r5[11:6]<DrvP> */
|
|
|
|
/* Get the final N locked value of driving strength [22:17] */
|
|
mov r5, r6
|
|
mov r5, r5, LSL #9
|
|
mov r5, r5, LSR #26 /* r5[5:0]<DrvN> = r6[22:17]<LockN> */
|
|
orr r5, r5, r5, LSL #6 /* r5[11:6]<DrvP> = r5[5:0]<DrvN> */
|
|
|
|
/* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
|
|
orr r6, r6, r5
|
|
|
|
MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG)
|
|
|
|
|
|
/* DDR SDRAM Data Pads Calibration */
|
|
MV_REG_READ_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG)
|
|
|
|
/* Set Bit [31] to make the register writable */
|
|
orr r8, r6, #SDRAM_WR_EN
|
|
|
|
MV_REG_WRITE_ASM (r8, r5, SDRAM_DATA_PADS_CAL_REG)
|
|
|
|
bic r6, r6, #SDRAM_WR_EN /* Make register read-only */
|
|
bic r6, r6, #SDRAM_TUNE_EN /* Disable auto calibration */
|
|
bic r6, r6, #SDRAM_DRVN_MASK /* Clear r5[5:0]<DrvN> */
|
|
bic r6, r6, #SDRAM_DRVP_MASK /* Clear r5[11:6]<DrvP> */
|
|
|
|
/* Get the final N locked value of driving strength [22:17] */
|
|
mov r5, r6
|
|
mov r5, r5, LSL #9
|
|
mov r5, r5, LSR #26
|
|
orr r5, r5, r5, LSL #6 /* r5[5:0] = r6[22:17]<LockN> */
|
|
|
|
/* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
|
|
orr r6, r6, r5
|
|
|
|
MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG)
|
|
|
|
glMem2End:
|
|
/* Implement Guideline (GL# MEM-3) Drive Strength Value */
|
|
/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
|
|
|
|
/* Get SDRAM Config value */
|
|
MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG)
|
|
|
|
/* Get DIMM type */
|
|
tst r8, #SDRAM_DTYPE_DDR2
|
|
beq ddr1StrengthVal
|
|
|
|
ddr2StrengthVal:
|
|
ldr r4, =DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV
|
|
ldr r8, =DDR2_DATA_PAD_STRENGTH_TYPICAL_DV
|
|
b setDrvStrength
|
|
ddr1StrengthVal:
|
|
ldr r4, =DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV
|
|
ldr r8, =DDR1_DATA_PAD_STRENGTH_TYPICAL_DV
|
|
|
|
setDrvStrength:
|
|
/* DDR SDRAM Address/Control Pads Calibration */
|
|
MV_REG_READ_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG)
|
|
|
|
orr r6, r6, #SDRAM_WR_EN /* Make register writeable */
|
|
|
|
MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG)
|
|
HTOLL(r6,r5)
|
|
|
|
bic r6, r6, #SDRAM_WR_EN /* Make register read-only */
|
|
bic r6, r6, #SDRAM_PRE_DRIVER_STRENGTH_MASK
|
|
orr r6, r4, r6 /* Set default value for DDR */
|
|
|
|
MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG)
|
|
|
|
|
|
/* DDR SDRAM Data Pads Calibration */
|
|
MV_REG_READ_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG)
|
|
|
|
orr r6, r6, #SDRAM_WR_EN /* Make register writeable */
|
|
|
|
MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG)
|
|
HTOLL(r6,r5)
|
|
|
|
bic r6, r6, #SDRAM_WR_EN /* Make register read-only */
|
|
bic r6, r6, #SDRAM_PRE_DRIVER_STRENGTH_MASK
|
|
orr r6, r8, r6 /* Set default value for DDR */
|
|
|
|
MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG)
|
|
|
|
|
|
/* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */
|
|
/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
|
|
/* Get the "sample on reset" register for the DDR frequancy */
|
|
|
|
#if defined(MV_RUN_FROM_FLASH)
|
|
/* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */
|
|
ldr r7, = _cpuARMDDRCLK
|
|
ldr r4, =_start
|
|
ldr r4, [r4]
|
|
sub r7, r7, r4
|
|
ldr r4, = Lrom_start_of_data
|
|
ldr r4, [r4]
|
|
add r7, r4, r7
|
|
#else
|
|
/* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */
|
|
ldr r7, = _cpuARMDDRCLK
|
|
ldr r4, =_start
|
|
sub r7, r7, r4
|
|
add r7, r7, #CFG_MONITOR_BASE
|
|
#endif
|
|
/* Get the "sample on reset" register for the DDR frequancy */
|
|
MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET)
|
|
ldr r5, =MSAR_ARMDDRCLCK_MASK
|
|
and r5, r4, r5
|
|
#if 0 /* YOTAM TO BE FIX */
|
|
mov r5, r5, LSR #MSAR_ARMDDRCLCK_OFFS
|
|
#endif
|
|
|
|
/* Read device ID */
|
|
MV_CTRL_MODEL_GET_ASM(r6, r8);
|
|
|
|
/* Continue if TC90 */
|
|
ldr r8, =MV_1281_DEV_ID
|
|
cmp r6, r6
|
|
beq armClkMsb
|
|
|
|
/* Continue if Orion2 */
|
|
ldr r8, =MV_5281_DEV_ID
|
|
cmp r6, r8
|
|
#if 0 /* YOTAM TO BE FIX */
|
|
bne 1f
|
|
#endif
|
|
|
|
armClkMsb:
|
|
#if 0 /* YOTAM TO BE FIX */
|
|
tst r4, #MSAR_ARMDDRCLCK_H_MASK
|
|
beq 1f
|
|
orr r5, r5, #BIT4
|
|
1:
|
|
ldr r4, =MV_CPU_ARM_CLK_ELM_SIZE
|
|
mul r5, r4, r5
|
|
add r7, r7, r5
|
|
add r7, r7, #MV_CPU_ARM_CLK_DDR_OFF
|
|
ldr r5, [r7]
|
|
#endif
|
|
|
|
/* Get SDRAM Config value */
|
|
MV_REG_READ_ASM (r8, r4, SDRAM_CONFIG_REG)
|
|
|
|
/* Get DIMM type */
|
|
tst r8, #SDRAM_DTYPE_DDR2
|
|
beq ddr1FtdllVal
|
|
|
|
ddr2FtdllVal:
|
|
ldr r4, =FTDLL_DDR2_250MHZ
|
|
ldr r7, =_250MHz
|
|
cmp r5, r7
|
|
beq setFtdllReg
|
|
ldr r4, =FTDLL_DDR2_200MHZ
|
|
ldr r7, =_200MHz
|
|
cmp r5, r7
|
|
beq setFtdllReg
|
|
ldr r4, =FTDLL_DDR2_166MHZ
|
|
ldr r7, =_166MHz
|
|
cmp r5, r7
|
|
beq setFtdllReg
|
|
ldr r4, =FTDLL_DDR2_133MHZ
|
|
b setFtdllReg
|
|
|
|
ddr1FtdllVal:
|
|
ldr r4, =FTDLL_DDR1_200MHZ
|
|
ldr r7, =_200MHz
|
|
cmp r5, r7
|
|
beq setFtdllReg
|
|
ldr r4, =FTDLL_DDR1_166MHZ
|
|
ldr r7, =_166MHz
|
|
cmp r5, r7
|
|
beq setFtdllReg
|
|
ldr r4, =FTDLL_DDR1_133MHZ
|
|
ldr r7, =_133MHz
|
|
cmp r5, r7
|
|
beq setFtdllReg
|
|
ldr r4, =0
|
|
|
|
setFtdllReg:
|
|
|
|
#if !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L)
|
|
MV_REG_READ_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG)
|
|
orr r8, r8, r4
|
|
MV_REG_WRITE_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG)
|
|
bic r8, r8, #1
|
|
MV_REG_WRITE_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG)
|
|
#endif /* !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L)*/
|
|
|
|
|
|
setTimingReg:
|
|
/* Set default Timing parameters */
|
|
MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG)
|
|
tst r8, #SDRAM_DTYPE_DDR2
|
|
bne ddr2TimeParam
|
|
|
|
ddr1TimeParam:
|
|
ldr r6, =DDR1_TIMING_LOW_DV
|
|
MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_LOW_REG)
|
|
ldr r6, =DDR1_TIMING_HIGH_DV
|
|
MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG)
|
|
b timeParamDone
|
|
|
|
ddr2TimeParam:
|
|
ldr r6, =DDR2_TIMING_LOW_DV
|
|
MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_LOW_REG)
|
|
ldr r6, =DDR2_TIMING_HIGH_DV
|
|
MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG)
|
|
|
|
timeParamDone:
|
|
/* Open CS[0] window to requested size and enable it. Disable other */
|
|
/* windows */
|
|
ldr r6, =SCBAR_BASE_MASK
|
|
sub r3, r3, #1
|
|
and r3, r3, r6
|
|
orr r3, r3, #1 /* Enable bank */
|
|
MV_REG_WRITE_ASM (r3, r5, SDRAM_SIZE_REG(0))
|
|
ldr r6, =0
|
|
MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(1))
|
|
MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(2))
|
|
MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(3))
|
|
|
|
exit_ddrAutoConfig:
|
|
mov PC, r11 /* r11 is saved link register */
|
|
|
|
|
|
/***************************************************************************************/
|
|
/* r4 holds I2C EEPROM address
|
|
* r7 holds I2C EEPROM offset parameter for i2cRead and its --> returned value
|
|
* r8 holds SDRAM various configuration registers value.
|
|
* r13 holds Link register
|
|
*/
|
|
/**************************/
|
|
_getDensity:
|
|
mov r13, LR /* Save link register */
|
|
|
|
mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
|
|
mov r7, #NUM_OF_ROWS_OFFSET /* offset 3 */
|
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bl _i2cRead
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mov r8, r7 /* r8 save number of rows */
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|
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mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
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mov r7, #NUM_OF_COLS_OFFSET /* offset 4 */
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bl _i2cRead
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add r8, r8, r7 /* r8 = number of rows + number of col */
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|
|
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mov r7, #0x1
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mov r8, r7, LSL r8 /* r8 = (1 << r8) */
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|
|
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mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
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mov r7, #SDRAM_WIDTH_OFFSET /* offset 13 */
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|
bl _i2cRead
|
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mul r8, r7, r8
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|
|
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mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
|
|
mov r7, #NUM_OF_BANKS_OFFSET /* offset 17 */
|
|
bl _i2cRead
|
|
mul r7, r8, r7
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|
|
|
mov PC, r13
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|
|
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/**************************/
|
|
_get_width:
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mov r13, LR /* Save link register */
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|
|
|
/* Get SDRAM width (SPD offset 13) */
|
|
mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
|
|
mov r7, #SDRAM_WIDTH_OFFSET
|
|
bl _i2cRead /* result in r7 */
|
|
|
|
mov PC, r13
|
|
|
|
/**************************/
|
|
_get_CAL:
|
|
mov r13, LR /* Save link register */
|
|
|
|
/* Set maximum CL supported by DIMM */
|
|
mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
|
|
mov r7, #SUPPORTED_CL_OFFSET /* offset 18 */
|
|
bl _i2cRead
|
|
|
|
mov PC, r13
|
|
|
|
/**************************/
|
|
/* R8 - sdram configuration register.
|
|
* Return value in flag if no-registered then Z-flag is set
|
|
*/
|
|
_is_Registered:
|
|
mov r13, LR /* Save link register */
|
|
|
|
/* Get registered/non registered info from DIMM */
|
|
tst r8, #SDRAM_DTYPE_DDR2
|
|
bne regDdr2
|
|
|
|
regDdr1:
|
|
mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
|
|
mov r7, #SDRAM_MODULES_ATTR_OFFSET
|
|
bl _i2cRead /* result in r7 */
|
|
tst r7, #0x2
|
|
b exit
|
|
regDdr2:
|
|
mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
|
|
mov r7, #DIMM_TYPE_INFO_OFFSET
|
|
bl _i2cRead /* result in r7 */
|
|
tst r7, #0x11 /* DIMM type = regular RDIMM (0x01) */
|
|
/* or Mini-RDIMM (0x10) */
|
|
exit:
|
|
mov PC, r13
|
|
|
|
|
|
#endif
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