193 lines
7.7 KiB
C
193 lines
7.7 KiB
C
/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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This software file (the "File") is owned and distributed by Marvell
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International Ltd. and/or its affiliates ("Marvell") under the following
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alternative licensing terms. Once you have made an election to distribute the
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File under one of the following license alternatives, please (i) delete this
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introductory statement regarding license alternatives, (ii) delete the two
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license alternatives that you have not elected to use and (iii) preserve the
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Marvell copyright notice above.
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********************************************************************************
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Marvell Commercial License Option
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If you received this File from Marvell and you have entered into a commercial
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license agreement (a "Commercial License") with Marvell, the File is licensed
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to you under the terms of the applicable Commercial License.
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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********************************************************************************
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Marvell BSD License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File under the following licensing terms.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Marvell nor the names of its contributors may be
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used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#ifndef __INCmvDramIfConfigh
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#define __INCmvDramIfConfigh
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/* includes */
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/* defines */
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/* registers defaults values */
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#define SDRAM_CONFIG_DV \
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(SDRAM_PERR_WRITE | \
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SDRAM_SRMODE | \
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SDRAM_SRCLK_GATED)
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#define SDRAM_DUNIT_CTRL_LOW_DV \
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(SDRAM_CTRL_POS_RISE | \
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SDRAM_CLK1DRV_NORMAL | \
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SDRAM_LOCKEN_ENABLE)
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#define SDRAM_ADDR_CTRL_DV 0
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#define SDRAM_TIMING_CTRL_LOW_REG_DV \
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((0x2 << SDRAM_TRCD_OFFS) | \
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(0x2 << SDRAM_TRP_OFFS) | \
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(0x1 << SDRAM_TWR_OFFS) | \
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(0x0 << SDRAM_TWTR_OFFS) | \
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(0x5 << SDRAM_TRAS_OFFS) | \
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(0x1 << SDRAM_TRRD_OFFS))
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/* TRFC 0x27, TW2W 0x1 */
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#define SDRAM_TIMING_CTRL_HIGH_REG_DV (( 0x7 << SDRAM_TRFC_OFFS ) |\
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( 0x2 << SDRAM_TRFC_EXT_OFFS) |\
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( 0x1 << SDRAM_TW2W_OFFS))
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#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN
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/* DDR2 ODT default register values */
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/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */
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/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */
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/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */
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/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */
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/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */
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/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */
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/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */
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#define DDR2_ODT_CTRL_LOW_CS0_DV 0x84210000
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#define DDR2_ODT_CTRL_HIGH_CS0_DV 0x00000000
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#define DDR2_DUNIT_ODT_CTRL_CS0_DV 0x0000780F
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#define DDR_SDRAM_EXT_MODE_CS0_DV 0x00000440
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#define DDR2_ODT_CTRL_LOW_CS0_CS2_DV 0x030C030C
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#define DDR2_ODT_CTRL_HIGH_CS0_CS2_DV 0x00000000
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#define DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV 0x0000740F
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#define DDR_SDRAM_EXT_MODE_CS0_CS2_DV 0x00000404
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/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */
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#define DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \
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(1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS)
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#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \
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(3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS)
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#define DDR1_DATA_PAD_STRENGTH_TYPICAL_DV \
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(1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS)
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#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \
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(3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS)
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/* DDR SDRAM Mode Register default value */
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#define DDR1_MODE_REG_DV 0x00000000
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#define DDR2_MODE_REG_DV 0x00000400
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/* DDR SDRAM Timing parameter default values */
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#define DDR1_TIMING_LOW_DV 0x11602220
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#define DDR1_TIMING_HIGH_DV 0x0000000d
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#define DDR2_TIMING_LOW_DV 0x11812220
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#define DDR2_TIMING_HIGH_DV 0x0000030f
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/* For Guideline (GL# MEM-4) DQS Reference Delay Tuning */
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#define FTDLL_DDR1_166MHZ ((0x1 << 0) | \
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(0x7F<< 12) | \
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(0x1 << 22))
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#define FTDLL_DDR1_133MHZ FTDLL_DDR1_166MHZ
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#define FTDLL_DDR1_200MHZ ((0x1 << 0) | \
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(0x1 << 12) | \
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(0x3 << 14) | \
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(0x1 << 18) | \
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(0x1 << 22))
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#define FTDLL_DDR2_166MHZ ((0x1 << 0) | \
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(0x1 << 12) | \
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(0x1 << 14) | \
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(0x1 << 16) | \
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(0x1 << 19) | \
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(0xF << 20))
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#define FTDLL_DDR2_133MHZ FTDLL_DDR2_166MHZ
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#define FTDLL_DDR2_200MHZ ((0x1 << 0) | \
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(0x1 << 12) | \
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(0x1 << 14) | \
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(0x1 << 16) | \
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(0x1 << 19) | \
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(0xF << 20))
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#define FTDLL_DDR2_250MHZ 0x445001
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/* Orion 1 B1 and above */
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#define FTDLL_DDR1_166MHZ_5181_B1 0x45D001
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/* Orion nas */
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#define FTDLL_DDR2_166MHZ_5182 0x597001
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/* Orion 2 D0 and above */
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#define FTDLL_DDR1_166MHZ_5281_D0 0x8D0001
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#define FTDLL_DDR1_200MHZ_5281_D0 0x8D0001
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#define FTDLL_DDR2_166MHZ_5281_D0 0x485001
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#define FTDLL_DDR2_200MHZ_5281_D0 0x485001
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#define FTDLL_DDR2_250MHZ_5281_D0 0x445001
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#define FTDLL_DDR2_200MHZ_5281_D1 0x995001
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#define FTDLL_DDR2_250MHZ_5281_D1 0x984801
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#endif /* __INCmvDramIfh */
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