414 lines
12 KiB
C
414 lines
12 KiB
C
/****************************************************************************
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*
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* SciTech OS Portability Manager Library
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*
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* ========================================================================
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*
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* The contents of this file are subject to the SciTech MGL Public
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* License Version 1.0 (the "License"); you may not use this file
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* except in compliance with the License. You may obtain a copy of
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* the License at http://www.scitechsoft.com/mgl-license.txt
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*
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* Software distributed under the License is distributed on an
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* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
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* implied. See the License for the specific language governing
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* rights and limitations under the License.
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*
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* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
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*
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* The Initial Developer of the Original Code is SciTech Software, Inc.
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* All Rights Reserved.
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*
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* ========================================================================
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*
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* Language: ANSI C
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* Environment: Any
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*
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* Description: Header file for interface routines to the PCI bus.
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*
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****************************************************************************/
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#ifndef __PCILIB_H
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#define __PCILIB_H
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#include "scitech.h"
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/*---------------------- Macros and type definitions ----------------------*/
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#pragma pack(1)
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/* Defines for PCIDeviceInfo.HeaderType */
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typedef enum {
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PCI_deviceType = 0x00,
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PCI_bridgeType = 0x01,
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PCI_cardBusBridgeType = 0x02,
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PCI_multiFunctionType = 0x80
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} PCIHeaderTypeFlags;
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/* Defines for PCIDeviceInfo.Command */
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typedef enum {
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PCI_enableIOSpace = 0x0001,
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PCI_enableMemorySpace = 0x0002,
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PCI_enableBusMaster = 0x0004,
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PCI_enableSpecialCylces = 0x0008,
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PCI_enableWriteAndInvalidate = 0x0010,
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PCI_enableVGACompatiblePalette = 0x0020,
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PCI_enableParity = 0x0040,
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PCI_enableWaitCycle = 0x0080,
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PCI_enableSerr = 0x0100,
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PCI_enableFastBackToBack = 0x0200
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} PCICommandFlags;
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/* Defines for PCIDeviceInfo.Status */
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typedef enum {
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PCI_statusCapabilitiesList = 0x0010,
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PCI_status66MhzCapable = 0x0020,
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PCI_statusUDFSupported = 0x0040,
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PCI_statusFastBackToBack = 0x0080,
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PCI_statusDataParityDetected = 0x0100,
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PCI_statusDevSel = 0x0600,
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PCI_statusSignaledTargetAbort = 0x0800,
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PCI_statusRecievedTargetAbort = 0x1000,
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PCI_statusRecievedMasterAbort = 0x2000,
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PCI_statusSignaledSystemError = 0x4000,
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PCI_statusDetectedParityError = 0x8000
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} PCIStatusFlags;
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/* PCI capability IDs */
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typedef enum {
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PCI_capsPowerManagement = 0x01,
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PCI_capsAGP = 0x02,
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PCI_capsMSI = 0x05
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} PCICapsType;
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/* PCI AGP rate definitions */
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typedef enum {
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PCI_AGPRate1X = 0x1,
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PCI_AGPRate2X = 0x2,
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PCI_AGPRate4X = 0x4
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} PCIAGPRateType;
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/* NOTE: We define all bitfield's as uint's, specifically so that the IBM
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* Visual Age C++ compiler does not complain. We need them to be
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* 32-bits wide, and this is the width of an unsigned integer, but
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* we can't use a ulong to make this explicit or we get errors.
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*/
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/* Structure defining a PCI slot identifier */
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typedef union {
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struct {
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uint Zero:2;
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uint Register:6;
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uint Function:3;
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uint Device:5;
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uint Bus:8;
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uint Reserved:7;
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uint Enable:1;
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} p;
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ulong i;
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} PCIslot;
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/* Structure defining the regular (type 0) PCI configuration register
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* layout. We use this in a union below so we can describe all types of
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* PCI configuration spaces with a single structure.
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*/
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typedef struct {
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ulong BaseAddress10;
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ulong BaseAddress14;
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ulong BaseAddress18;
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ulong BaseAddress1C;
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ulong BaseAddress20;
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ulong BaseAddress24;
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ulong CardbusCISPointer;
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ushort SubSystemVendorID;
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ushort SubSystemID;
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ulong ROMBaseAddress;
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uchar CapabilitiesPointer;
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uchar reserved1;
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uchar reserved2;
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uchar reserved3;
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ulong reserved4;
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uchar InterruptLine;
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uchar InterruptPin;
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uchar MinimumGrant;
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uchar MaximumLatency;
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/* These are not in the actual config space, but we enumerate them */
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ulong BaseAddress10Len;
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ulong BaseAddress14Len;
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ulong BaseAddress18Len;
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ulong BaseAddress1CLen;
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ulong BaseAddress20Len;
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ulong BaseAddress24Len;
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ulong ROMBaseAddressLen;
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} PCIType0Info;
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/* Structure defining PCI to PCI bridge (type 1) PCI configuration register
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* layout. We use this in a union below so we can describe all types of
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* PCI configuration spaces with a single structure.
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*/
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typedef struct {
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ulong BaseAddress10;
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ulong BaseAddress14;
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uchar PrimaryBusNumber;
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uchar SecondayBusNumber;
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uchar SubordinateBusNumber;
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uchar SecondaryLatencyTimer;
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uchar IOBase;
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uchar IOLimit;
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ushort SecondaryStatus;
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ushort MemoryBase;
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ushort MemoryLimit;
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ushort PrefetchableMemoryBase;
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ushort PrefetchableMemoryLimit;
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ulong PrefetchableBaseHi;
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ulong PrefetchableLimitHi;
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ushort IOBaseHi;
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ushort IOLimitHi;
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uchar CapabilitiesPointer;
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uchar reserved1;
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uchar reserved2;
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uchar reserved3;
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ulong ROMBaseAddress;
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uchar InterruptLine;
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uchar InterruptPin;
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ushort BridgeControl;
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} PCIType1Info;
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/* PCI to CardBus bridge (type 2) configuration information */
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typedef struct {
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ulong SocketRegistersBaseAddress;
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uchar CapabilitiesPointer;
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uchar reserved1;
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ushort SecondaryStatus;
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uchar PrimaryBus;
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uchar SecondaryBus;
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uchar SubordinateBus;
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uchar SecondaryLatency;
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struct {
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ulong Base;
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ulong Limit;
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} Range[4];
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uchar InterruptLine;
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uchar InterruptPin;
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ushort BridgeControl;
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} PCIType2Info;
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/* Structure defining the PCI configuration space information for a
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* single PCI device on the PCI bus. We enumerate all this information
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* for all PCI devices on the bus.
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*/
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typedef struct {
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ulong dwSize;
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PCIslot slot;
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ulong mech1;
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ushort VendorID;
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ushort DeviceID;
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ushort Command;
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ushort Status;
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uchar RevID;
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uchar Interface;
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uchar SubClass;
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uchar BaseClass;
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uchar CacheLineSize;
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uchar LatencyTimer;
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uchar HeaderType;
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uchar BIST;
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union {
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PCIType0Info type0;
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PCIType1Info type1;
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PCIType2Info type2;
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} u;
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} PCIDeviceInfo;
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/* PCI Capability header structure. All PCI capabilities have the
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* following header.
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*
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* capsID is used to identify the type of the structure as define above.
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*
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* next is the offset in PCI configuration space (0x40-0xFC) of the
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* next capability structure in the list, or 0x00 if there are no more
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* entries.
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*/
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typedef struct {
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uchar capsID;
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uchar next;
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} PCICapsHeader;
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/* Structure defining the PCI AGP status register contents */
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typedef struct {
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uint rate:3;
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uint rsvd1:1;
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uint fastWrite:1;
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uint fourGB:1;
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uint rsvd2:3;
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uint sideBandAddressing:1;
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uint rsvd3:14;
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uint requestQueueDepthMaximum:8;
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} PCIAGPStatus;
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/* Structure defining the PCI AGP command register contents */
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typedef struct {
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uint rate:3;
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uint rsvd1:1;
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uint fastWriteEnable:1;
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uint fourGBEnable:1;
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uint rsvd2:2;
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uint AGPEnable:1;
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uint SBAEnable:1;
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uint rsvd3:14;
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uint requestQueueDepth:8;
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} PCIAGPCommand;
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/* AGP Capability structure */
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typedef struct {
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PCICapsHeader h;
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ushort majMin;
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PCIAGPStatus AGPStatus;
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PCIAGPCommand AGPCommand;
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} PCIAGPCapability;
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/* Structure for obtaining the PCI IRQ routing information */
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typedef struct {
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uchar bus;
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uchar device;
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uchar linkA;
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ushort mapA;
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uchar linkB;
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ushort mapB;
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uchar linkC;
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ushort mapC;
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uchar linkD;
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ushort mapD;
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uchar slot;
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uchar reserved;
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} PCIRouteInfo;
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typedef struct {
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ushort BufferSize;
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PCIRouteInfo *DataBuffer;
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} PCIRoutingOptionsBuffer;
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#define NUM_PCI_REG (sizeof(PCIDeviceInfo) / 4) - 10
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#define PCI_BRIDGE_CLASS 0x06
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#define PCI_HOST_BRIDGE_SUBCLASS 0x00
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#define PCI_EARLY_VGA_CLASS 0x00
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#define PCI_EARLY_VGA_SUBCLASS 0x01
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#define PCI_DISPLAY_CLASS 0x03
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#define PCI_DISPLAY_VGA_SUBCLASS 0x00
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#define PCI_DISPLAY_XGA_SUBCLASS 0x01
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#define PCI_DISPLAY_OTHER_SUBCLASS 0x80
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#define PCI_MM_CLASS 0x04
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#define PCI_AUDIO_SUBCLASS 0x01
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/* Macros to detect specific classes of devices */
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#define PCI_IS_3DLABS_NONVGA_CLASS(pci) \
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(((pci)->BaseClass == PCI_DISPLAY_CLASS && (pci)->SubClass == PCI_DISPLAY_OTHER_SUBCLASS) \
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&& ((pci)->VendorID == 0x3D3D || (pci)->VendorID == 0x104C))
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#define PCI_IS_DISPLAY_CLASS(pci) \
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(((pci)->BaseClass == PCI_DISPLAY_CLASS && (pci)->SubClass == PCI_DISPLAY_VGA_SUBCLASS) \
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|| ((pci)->BaseClass == PCI_DISPLAY_CLASS && (pci)->SubClass == PCI_DISPLAY_XGA_SUBCLASS) \
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|| ((pci)->BaseClass == PCI_EARLY_VGA_CLASS && (pci)->SubClass == PCI_EARLY_VGA_SUBCLASS) \
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|| PCI_IS_3DLABS_NONVGA_CLASS(pci))
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/* Function codes to pass to PCI_accessReg */
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#define PCI_READ_BYTE 0
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#define PCI_READ_WORD 1
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#define PCI_READ_DWORD 2
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#define PCI_WRITE_BYTE 3
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#define PCI_WRITE_WORD 4
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#define PCI_WRITE_DWORD 5
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/* Macros to read/write PCI registers. These assume a global PCI array
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* of device information.
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*/
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#define PCI_readPCIRegB(index,device) \
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PCI_accessReg(index,0,0,&PCI[DeviceIndex[device]])
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#define PCI_readPCIRegW(index,device) \
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PCI_accessReg(index,0,1,&PCI[DeviceIndex[device]])
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#define PCI_readPCIRegL(index,device) \
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PCI_accessReg(index,0,2,&PCI[DeviceIndex[device]])
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#define PCI_writePCIRegB(index,value,device) \
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PCI_accessReg(index,value,3,&PCI[DeviceIndex[device]])
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#define PCI_writePCIRegW(index,value,device) \
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PCI_accessReg(index,value,4,&PCI[DeviceIndex[device]])
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#define PCI_writePCIRegL(index,value,device) \
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PCI_accessReg(index,value,5,&PCI[DeviceIndex[device]])
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#pragma pack()
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/*-------------------------- Function Prototypes --------------------------*/
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#ifdef __cplusplus
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extern "C" { /* Use "C" linkage when in C++ mode */
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#endif
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/* Function to determine the number of PCI devices in the system */
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int _ASMAPI PCI_getNumDevices(void);
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/* Function to enumerate all device on the PCI bus */
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int _ASMAPI PCI_enumerate(PCIDeviceInfo info[]);
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/* Function to access PCI configuration registers */
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ulong _ASMAPI PCI_accessReg(int index,ulong value,int func,PCIDeviceInfo *info);
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/* Function to get PCI IRQ routing options for a card */
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int _ASMAPI PCI_getIRQRoutingOptions(int numDevices,PCIRouteInfo *buffer);
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/* Function to re-route the PCI IRQ setting for a device */
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ibool _ASMAPI PCI_setHardwareIRQ(PCIDeviceInfo *info,uint intPin,uint IRQ);
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/* Function to generate a special cyle on the specified PCI bus */
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void _ASMAPI PCI_generateSpecialCyle(uint bus,ulong specialCycleData);
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/* Function to determine the size of a PCI base address register */
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ulong _ASMAPI PCI_findBARSize(int bar,PCIDeviceInfo *pci);
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/* Function to read a block of PCI configuration space registers */
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void _ASMAPI PCI_readRegBlock(PCIDeviceInfo *info,int index,void *dst,int count);
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/* Function to write a block of PCI configuration space registers */
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void _ASMAPI PCI_writeRegBlock(PCIDeviceInfo *info,int index,void *src,int count);
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/* Function to return the 32-bit PCI BIOS entry point */
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ulong _ASMAPI PCIBIOS_getEntry(void);
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#ifdef __cplusplus
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} /* End of "C" linkage for C++ */
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#endif
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#endif /* __PCILIB_H */
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